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IEEE Computer Architecture Letters

Issue 1 • January-June 2013

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Displaying Results 1 - 13 of 13
  • Introducing the New Editor-in-Chief of the IEEE Computer Architecture Letters

    Publication Year: 2013, Page(s): 1
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  • A Message from the New Editor-in-Chief and Introduction of New Associate Editors

    Publication Year: 2013, Page(s):2 - 4
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  • Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs

    Publication Year: 2013, Page(s):5 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (778 KB) | HTML iconHTML

    In recent years, flash memory solid state disks (SSDs) have shown a great potential to change storage infrastructure because of its advantages of high speed and high throughput random access. This promising storage, however, greatly suffers from performance loss because of frequent ``erase-before-write'' and ``garbage collection'' operations. Thus, novel circuit-level, architectural, and algorithm... View full abstract»

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  • A New Worst-Case Throughput Bound for Oblivious Routing in Odd Radix Mesh Network

    Publication Year: 2013, Page(s):9 - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    1/2 network capacity is often believed to be the limit of worst-case throughput for mesh networks. However, this letter provides a new worst-case throughput bound, which is higher than 1/2 network capacity, for odd radix two-dimensional mesh networks. In addition, we propose a routing algorithm called U2TURN that can achieve this worst-case throughput bound. U2TURN considers all routing paths with... View full abstract»

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  • Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values

    Publication Year: 2013, Page(s):13 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB) | HTML iconHTML

    Soft errors are transient errors that can alter the logic value of a register bit causing data corruption. They can be caused by radiation particles such as neutrons or alpha particles. Narrow values are commonly found in the data consumed or produced by processors. Several techniques have recently been proposed to exploit the unused bits in narrow values to protect them against soft errors. These... View full abstract»

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  • Shrink-Fit: A Framework for Flexible Accelerator Sizing

    Publication Year: 2013, Page(s):17 - 20
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (626 KB) | HTML iconHTML

    RTL design complexity discouraged adoption of reconfigurable logic in general purpose systems, impeding opportunities for performance and energy improvements. Recent improvements to HLS compilers simplify RTL design and are easing this barrier. A new challenge will emerge: managing reconfigurable resources between multiple applications with custom hardware designs. In this paper, we propose a meth... View full abstract»

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  • Compiler-assisted, selective out-of-order commit

    Publication Year: 2013, Page(s):21 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (705 KB) | HTML iconHTML

    This paper proposes an out-of-order instruction commit mechanism using a novel compiler/architecture interface. The compiler creates instruction “blocks” guaranteeing some commit conditions and the processor uses the block information to commit certain instructions out of order. Micro-architectural support for the new commit mode is made on top of the standard, ROB-based processor an... View full abstract»

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  • Metrics for Early-Stage Modeling of Many-Accelerator Architectures

    Publication Year: 2013, Page(s):25 - 28
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (13263 KB)

    The term “Dark Silicon” has been coined to describe the threat to microprocessor performance caused by increasing transistor power density. Improving energy efficiency is now the primary design goal for all market segments of microprocessors from mobile to server. Specialized hardware accelerators, designed to run only a subset of workloads with orders of magnitude energy efficiency ... View full abstract»

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  • The Netflix Challenge: Datacenter Edition

    Publication Year: 2013, Page(s):29 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24948 KB)

    The hundreds of thousands of servers in modern warehouse-scale systems make performance and efficiency optimizations pressing design challenges. These systems are traditionally considered homogeneous. However, that is not typically the case. Multiple server generations compose a heterogeneous environment, whose performance opportunities have not been fully explored since techniques that account fo... View full abstract»

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  • 2012 reviewers list

    Publication Year: 2013, Page(s):33 - 34
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  • IEEE Open Access Publishing

    Publication Year: 2013, Page(s): 35
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  • IEEE Transactions Newsletter

    Publication Year: 2013, Page(s): 36
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  • 2012 Annual Index

    Publication Year: 2013, Page(s):1 - 4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
José Martinez
Cornell University
336 Frank H.T. Rhodes Hall
Ithaca, NY 14853 USA
e-mail: martinez@cornell.edu