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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 12 • Dec 1993

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Displaying Results 1 - 16 of 16
  • A novel behavioral testability measure

    Publication Year: 1993, Page(s):1960 - 1970
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (904 KB)

    In this paper a new approach, called BETA, for computing testability is presented. The approach is based on analyzing the circuit's behavioral description: the control flow graph (CFG). Based on path analysis, testability measures are derived. Unlike a traditional testability measure which computes testability, our approach also derives the exact sequence for justifying and propagating the content... View full abstract»

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  • Verification of relations between synchronous machines

    Publication Year: 1993, Page(s):1947 - 1959
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (992 KB)

    Uses string function theory to develop an efficient methodology for the verification of logic implementations against behavioral specifications. First, the authors define five primitive relations between string functions, other than strict automata equivalence, namely: don't care times, parallelism, encoding, input don't care and output don't care relations. These relations have attributes, For in... View full abstract»

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  • A multiple-strength multiple-delay compiled-code logic simulator

    Publication Year: 1993, Page(s):1937 - 1946
    Cited by:  Papers (2)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (996 KB)

    Describes a new logic state model for gate level simulation based upon a powerset representation of the possible drive states at the output of a logic gate. Efficient implementation techniques for this model in a compiled-code logic simulator are presented, with the results that most complicated operations can be optimized into simple table lookups. Algorithmic issues in a multiple-strength multip... View full abstract»

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  • A delay-based model for circuit parallelism

    Publication Year: 1993, Page(s):1903 - 1912
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB)

    A new formal model for variable-delay simulators is presented for comparing the effects of time base on circuit parallelism. This model more accurately reflects current simulation strategies than previous models. Using this new model the author shows that parallelism is not a nondecreasing function of time base. She bounds parallelism, however, by two functions that converge to the unit-delay para... View full abstract»

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  • Efficient via shifting algorithms in channel compaction

    Publication Year: 1993, Page(s):1848 - 1857
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    Considers in this paper the problem of shifting vias to obtain more compactable channel routing solutions. Let S be a grid-based two-layer channel routing solution. Let vc, wc be the number of grid points on column c that are occupied by vias, horizontal wires in S, respectively. The authors define the expected height of columns c in S to be hc=Avc+Bw... View full abstract»

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  • Computation of floating mode delay in combinational circuits: practice and implementation

    Publication Year: 1993, Page(s):1924 - 1936
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB)

    Delay computation in combinational logic circuits is complicated by the existence of unsensitizable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but the authors use a recently developed single-vector condition, t... View full abstract»

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  • Capacitance of top leads metal - comparison between formula, simulation, and experiment

    Publication Year: 1993, Page(s):1897 - 1902
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    The parasitic interconnection capacitance can significantly degrade the performance of an IC. In this paper, the parasitic capacitance of the top leads with a protective overcoat (PO) dielectric is modeled. For a nitride only PO, the nitride increases the line-to-line capacitance component by the average of the nitride and underlying oxide dielectric constants with a maximum error of 11% according... View full abstract»

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  • Interpolation of MOSFET table data in width, length, and temperature

    Publication Year: 1993, Page(s):1880 - 1884
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Table-based transistor modeling techniques require a current table and a charge/capacitance table for each device geometry at each simulation temperature. Simple interpolation methods can be used to construct any current table from a small basis set of tables. A database of 32 current tables (two widths, four lengths, measured at four temperatures) is sufficient to span the space defined by these ... View full abstract»

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  • An efficient algorithm for bipartite PLA folding

    Publication Year: 1993, Page(s):1839 - 1847
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    Programmable logic arrays (PLAs) provide a flexible and efficient way of synthesizing arbitrary combinational functions as well as sequential logic circuits. They are used in both LSI and VLSI technologies. The disadvantage of using PLAs is that most PLAs are very sparse. The high sparsity of the PLA results in a significant waste of silicon area. PLA folding is a technique which reclaims unused a... View full abstract»

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  • Transition fault testing for sequential circuits

    Publication Year: 1993, Page(s):1971 - 1983
    Cited by:  Papers (62)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB)

    Addresses the problem of simulating and generating tests for transition faults in nonscan and partial scan synchronous sequential circuits. A transition fault model for sequential circuits is first proposed. In this fault model, a transition fault is characterized by the fault site, the fault type, and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specifi... View full abstract»

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  • Computation of floating mode delay in combinational circuits: theory and algorithms

    Publication Year: 1993, Page(s):1913 - 1923
    Cited by:  Papers (54)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB)

    Addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at the inputs.) It is well known that using the length of the topologically longest path as an estimate of circuit delay may be pessimistic since this path may be false, i.e., it canno... View full abstract»

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  • A unified approach to floorplan sizing and enumeration

    Publication Year: 1993, Page(s):1858 - 1867
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (784 KB)

    Given a sliceable floorplan and cell sizes, Otten and Stockmeyer [1983] presented an algorithm to find an optimal implementation for each cell. The authors consider a generalized optimal sizing problem on a set of slicing trees related to an adjacency graph. For computation efficiency, they combine the tree enumeration and sizing procedures in a unified algorithm where floorplan trees and sizes ar... View full abstract»

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  • An efficient algorithm for constrained encoding and its applications

    Publication Year: 1993, Page(s):1813 - 1826
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1164 KB)

    An efficient algorithm and its implementation, ENCORE, are presented for finding approximate solutions to dichotomy-based constrained encoding, a problem fundamental to the synthesis of combinational logic circuits, and synchronous and asynchronous sequential circuits. ENCORE adopts a greedy strategy to find an encoding bit by bit, and then uses an iterative method to improve the solution quality.... View full abstract»

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  • Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors

    Publication Year: 1993, Page(s):1885 - 1896
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1060 KB)

    Gallium arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper studies the behavior of gallium arsenide high electron mobility transistor (HEMT) memories in the presence of material defects, processing errors and design errors to formulate efficient testing schemes. All d... View full abstract»

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  • Integrated circuit quality optimization using surface integrals

    Publication Year: 1993, Page(s):1868 - 1879
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1048 KB)

    A novel formulation of the parametric yield as a surface integral on the boundary of the disturbance space acceptability region is introduced. This formulation allows the accurate and efficient estimation of yield via a Monte Carlo method which can also produce yield gradients with minimal overhead. The authors extend this formulation to a more general IC quality measure. A general IC quality opti... View full abstract»

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  • A stochastic model to predict the routability of field-programmable gate arrays

    Publication Year: 1993, Page(s):1827 - 1838
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1044 KB)

    One area of particular importance is the design of an FPGA routing architecture, which houses the user-programmable switches and wires that are used to interconnect the FPGAs logic resources. Because the routing switches consume significant chip area and introduce propagation delays, the design of the routing architecture greatly influences both the area utilization and speed performance of an FPG... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu