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IEEE Transactions on Circuits and Systems II: Express Briefs

Issue 6 • June 2011

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2011, Page(s): C1
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2011, Page(s): C2
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  • A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm

    Publication Year: 2011, Page(s):321 - 325
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB) | HTML iconHTML

    A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metal-oxide-semiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectiv... View full abstract»

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  • A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer

    Publication Year: 2011, Page(s):326 - 330
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (681 KB) | HTML iconHTML

    Flying-adder architecture is an emerging on-chip frequency synthesis technology. Its theoretical foundation is the time-average-frequency concept introduced in 2008. During the past decade, the flying-adder technique has been successfully used in numerous commercial products. However, when fractional control word is used, its clock spectrum contains spurious tones due to the periodic carries gener... View full abstract»

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  • Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

    Publication Year: 2011, Page(s):331 - 335
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (331 KB) | HTML iconHTML

    Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several digital BBPLLs (DBBPLLs) suitable for frequency synthesis. This brief investigates the effect of nonaccumulative reference clock jitter (due to white ph... View full abstract»

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  • A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency

    Publication Year: 2011, Page(s):336 - 340
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB) | HTML iconHTML

    This brief proposes an explicit Dickson charge pump model, including the effect of the resistance of switching devices on the pump performance. Using this model, one can estimate an optimum clock frequency and the size of the transferring transistors in terms of the main pump capacitors, the auxiliary capacitors, and the transfer transistors to maximize the output current under the same silicon ar... View full abstract»

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  • Predicting and Avoiding Spurious Tones in a DWA-Mismatch-Shaping DAC

    Publication Year: 2011, Page(s):341 - 345
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (339 KB) | HTML iconHTML

    A data-weighted-averaging (DWA) algorithm provides a simple realization of the first-order mismatch shaping of digital-to-analog-converter (DAC) errors. A drawback of DWA is the tendency for generating spurious tones. This brief proposes an analytical model for mismatch-noise tone behavior. The model explains how the spurious tones depend on the stimulus and the DAC error shape. It is also shown t... View full abstract»

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  • High-Order Mismatch-Shaping in Multibit DACs

    Publication Year: 2011, Page(s):346 - 350
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB) | HTML iconHTML

    This brief reports a high-order mismatch-shaping technique for multibit ΔΣ digital-to-analog converters (DACs). It builds upon the vector-based method but with two key improvements. First, a new vector quantization (VQ) scheme exploits the information in all vector variables. This VQ scheme allows the second-order mismatch shaping for large input signals and makes possible the stable... View full abstract»

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  • A Subhertz Nanopower Low-Pass Filter

    Publication Year: 2011, Page(s):351 - 355
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB) | HTML iconHTML

    This brief presents a first-order low-pass filter topology capable of providing cutoff frequencies down to 2 mHz with power consumption of 5 nW. The circuit is intended for signal conditioning applications, particularly for use with very low frequency physiological signals in low-power portable medical equipment. To achieve a low-frequency cutoff, the filter is based around the use of a clocked tr... View full abstract»

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  • An Electronically Fine-Tunable Multi-Input–Single-Output Universal Filter

    Publication Year: 2011, Page(s):356 - 360
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (353 KB) | HTML iconHTML

    A new electronically fine-tunable multi-input-single-output (MISO) universal filter is proposed. The filter circuit compared with active-device-based counterparts is very simple and fully integrable. Moreover, a few number of active transistors provide a reduction in power consumption, and the filter enjoys advantages such as no component matching and small size area. Postlayout simulation results... View full abstract»

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  • A Spread Spectrum Clock Generator for DisplayPort Main Link

    Publication Year: 2011, Page(s):361 - 365
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB) | HTML iconHTML

    This brief presents a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link. The process variation compensator reduces the error of spread ratio and guarantees reliable operation of an SSCG. The test chip has been implemented in 0.18-μm complementary metal-oxide-semiconductor process. The SSCG supports 10-phase 270- and 162-MHz clocks. The pha... View full abstract»

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  • Regularization of the Affine Projection Algorithm

    Publication Year: 2011, Page(s):366 - 370
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (374 KB) | HTML iconHTML

    The affine projection algorithm (APA) is an attractive choice for echo cancellation, mainly for its convergence features. A matrix inversion is required within the APA. For practical reasons, this matrix needs to be regularized, i.e., a positive constant is added to the elements of its main diagonal. This regularization parameter is of great importance in practice since, if it is not chosen proper... View full abstract»

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  • A Low-Complexity Flexible Spectrum-Sensing Scheme for Mobile Cognitive Radio Terminals

    Publication Year: 2011, Page(s):371 - 375
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (386 KB) | HTML iconHTML

    Low-complexity and flexible spectrum sensing is one of the challenging tasks in a cognitive radio (CR). Most of the work on energy-detection-based spectrum sensing presented in the literature employ a filter bank (FB) to split the wideband input signal into several subbands and detect the spectrum by computing the energy of subbands. However, for a mobile CR handset, a filter-bank-based spectrum s... View full abstract»

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  • Design of a Monolithic Automatic Substrate/Supply Multiplexer for DVS-Enabled Adaptive Power Converters

    Publication Year: 2011, Page(s):376 - 380
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (728 KB) | HTML iconHTML

    It allows the converters to seamlessly regulate the output voltage at any desired level without suffering large leakage current and latch-up. In addition, an automatic supply voltage multiplexing scheme is presented to significantly improve power efficiency and reduce chip area. The proposed ASSM circuit was fabricated with an IBM 130-nm CMOS process. Experimental results show a 4.44-mV/ns switchi... View full abstract»

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  • Study of Periodic Solutions in Discretized Two-Dimensional Sliding-Mode Control Systems

    Publication Year: 2011, Page(s):381 - 385
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB) | HTML iconHTML

    The existence of periodic solutions in discretized 2-D equivalent control-based sliding-mode control systems is studied. Admissibility conditions for the existence of periodic solutions with specific symbol sequences are derived, and admissibility regions for short periodic sequences are found. It is shown that, for certain parameter values, there exist arbitrarily long periodic orbits for arbitra... View full abstract»

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  • Passivity-Based Integral Sliding-Mode Control of Uncertain Singularly Perturbed Systems

    Publication Year: 2011, Page(s):386 - 390
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (214 KB) | HTML iconHTML

    This brief is concerned with passivity-based integral sliding-mode control of uncertain singularly perturbed systems. First, a proper integral sliding surface is constructed. Then, a sufficient condition in terms of linear matrix inequality (LMI) is derived under which the resulting closed-loop system is passive and asymptotically stable in the specified switching surface. The gain matrix of the s... View full abstract»

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  • 2011 IEEE membership form

    Publication Year: 2011, Page(s):391 - 392
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  • IEEE Circuits and Systems Society Information

    Publication Year: 2011, Page(s): C3
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Publication Year: 2011, Page(s): C4
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Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org