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IET Computers & Digital Techniques

Issue 5 • September 2010

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Displaying Results 1 - 8 of 8
  • Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

    Publication Year: 2010, Page(s):349 - 364
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1253 KB)

    A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily ha... View full abstract»

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  • Static test compaction for diagnostic test sets of full-scan circuits

    Publication Year: 2010, Page(s):365 - 373
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (171 KB)

    The authors describe a static test compaction procedure for diagnostic test sets of full-scan circuits. Similar to reverse order and random order fault simulation procedures applied to fault detection test sets, the procedure simulates the test set in different orders in order to identify unnecessary tests. Two features distinguish the procedure from earlier ones. (i) It uses a diagnostic fault si... View full abstract»

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  • Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains

    Publication Year: 2010, Page(s):374 - 387
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1028 KB)

    The exploration and design process of highly efficient processor element for multimedia and signal processing domains is presented in this study. With the introduction of synchronous data-transfer architecture for high-performance embedded applications, the effectively exploring the exponential-size architectural design spaces by detailed simulation is intractable. The authors attack this via an a... View full abstract»

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  • Robust intellectual property protection of VLSI physical design

    Publication Year: 2010, Page(s):388 - 399
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1052 KB)

    In deep sub-micron VLSI, increased demand for design productivity of ICs with millions of devices has led to widespread design reuse. This however enhances the probability of infringement of intellectual property (IP) of the design. Typically, repudiation attack by the IP owner through challenging the legality of the buyer and additive attack through insertion of additional marks in the design are... View full abstract»

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  • System-level power management for system-on-a-chip -based mobile devices

    Publication Year: 2010, Page(s):400 - 409
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (617 KB)

    Since power management policies tend to have limits when based on individual components of a system, such as the processor, memory or LCD, it is necessary to have a system-wide approach that considers power components in an integrated way. The system-on-a-chip (SoC) that has been commonly adopted in handheld devices is one system in particular that requires the close interactions among the compone... View full abstract»

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  • Low-power dual-edge triggered state-retention scan flip-flop

    Publication Year: 2010, Page(s):410 - 419
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1042 KB)

    This study presents a dual-edge triggered static scanable flip-flop suitable for low-power applications. The proposed circuit deploys reduced swing-clock and swing-data to manage dynamic power. Furthermore, it employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining its state. The static structure of the circuit makes it feasible to be us... View full abstract»

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  • Low-overhead single-event upset hardened latch using programmable resistance cells

    Publication Year: 2010, Page(s):420 - 427
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (376 KB)

    This study presents a single-event upset (SEU) hardened latch having first and second cross-coupled inverters and first and second programmable resistance metallisation cells. The metallisation cells may be programmed to low or high-resistance states. When set to a low-resistance state, the latch may be accessed to write a new logic state into the latch. When reset to a high-resistance state, the ... View full abstract»

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  • Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability

    Publication Year: 2010, Page(s):428 - 437
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (383 KB)

    This study presents a simplified structure of bit parallel systolic multiplier over Galois fields (GFs) over the set GF(2m) suitable for cryptographic hardware implementation. A redundant standard basis representation with the irreducible all one polynomial is considered. The systolic multiplier consists of (m+1)2 identical cells, each consisting of one two-input AND gate,... View full abstract»

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Aims & Scope

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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