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IEEE Transactions on Computers

Issue 3 • March 2010

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Displaying Results 1 - 16 of 16
  • [Front cover]

    Publication Year: 2010, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2010, Page(s): c2
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  • A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects

    Publication Year: 2010, Page(s):289 - 300
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3570 KB) | HTML iconHTML

    This paper presents a comprehensive framework for logic diagnosis consisting of two main phases. In the first phase, a set of suspected faulty sites is obtained by applying an approach based on an Effect-Cause analysis. Then, in the second phase, a set of realistic fault models is associated with each suspected faulty site by analyzing specific information, called fault evidences, collected during... View full abstract»

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  • Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques

    Publication Year: 2010, Page(s):301 - 316
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4375 KB) | HTML iconHTML

    This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests... View full abstract»

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  • The Design and Evaluation of a Self-Organizing Superpeer Network

    Publication Year: 2010, Page(s):317 - 331
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3086 KB) | HTML iconHTML

    Superpeer architectures exploit the heterogeneity of nodes in a peer-to-peer (P2P) network by assigning additional responsibilities to higher capacity nodes. In the design of a superpeer network for file sharing, several issues have to be addressed: how client peers are related to superpeers, how superpeers locate files, how the load is balanced among the superpeers, and how the system deals with ... View full abstract»

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  • Design and Analysis of On-Chip Networks for Large-Scale Cache Systems

    Publication Year: 2010, Page(s):332 - 344
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3834 KB) | HTML iconHTML

    Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may result in unnecessary high cost and low performance when the interconnects are not optimized for the domain. Designing an optimal network for the specific domain is challenging because in-depth knowledge of interconnects and t... View full abstract»

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  • ALV: A New Data Redistribution Approach to RAID-5 Scaling

    Publication Year: 2010, Page(s):345 - 357
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2688 KB) | HTML iconHTML

    When a RAID-5 volume is scaled up with added disks, data have to be redistributed from original disks to all disks including the original and the new. Existing online scaling techniques suffer from long redistribution times as well as negative impacts on application performance. By leveraging our insight into a reordering window, this paper presents ALV, a new data redistribution approach to RAID-... View full abstract»

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  • An Analytic Framework for Detailed Resource Profiling in Large and Parallel Programs and Its Application for Memory Use

    Publication Year: 2010, Page(s):358 - 370
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1451 KB) | HTML iconHTML

    Profiling is an essential and widely used technique to understand the resource use of applications. For example, the memory use of large applications is becoming an important cost factor. Very large systems are typically sized to accommodate designated tasks, and thus, the price, as well as cache and TLB efficiency, depends significantly on the memory footprint of the target applications. Importan... View full abstract»

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  • New Region-Based Algorithms for Deriving Bounded Petri Nets

    Publication Year: 2010, Page(s):371 - 384
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2888 KB) | HTML iconHTML

    The theory of regions was introduced in the early nineties as a method to bridge state and event-based models. This paper tackles the problem of deriving a Petri net from a state-based model, using the theory of regions. Some of the restrictions required in the traditional approach are dropped in this paper, together with significant extensions that make the approach applicable in new scenarios. O... View full abstract»

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  • CSMT: Simultaneous Multithreading for Clustered VLIW Processors

    Publication Year: 2010, Page(s):385 - 399
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4167 KB) | HTML iconHTML

    Simultaneous MultiThreading (SMT) is a well-known technique that improves resource utilization by exploiting thread-level parallelism at the instruction grain level. However, implementing SMT for VLIWs requires complex structures, which is contrary to the VLIW philosophy of hardware simplicity. In this paper, we propose Cluster-level Simultaneous MultiThreading (CSMT) to allow some degree of SMT i... View full abstract»

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  • Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems

    Publication Year: 2010, Page(s):400 - 415
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1321 KB) | HTML iconHTML

    The integration phase of real-time COTS-based systems is challenging. When multiple tasks run concurrently, the interference at the bus level between cache fetching activities and I/O peripheral transactions is significant and causes unpredictable behaviors: experimentally, we show that tasks can have computation time variance up to 46 percent in a typical embedded system. In this work, we present... View full abstract»

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  • QoS Control for Pipelines of Tasks Using Multiple Resources

    Publication Year: 2010, Page(s):416 - 430
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2142 KB) | HTML iconHTML Multimedia Media

    We consider soft real-time applications organized as pipelines of tasks using resources of different type (communication, computation, and storage). The applications are assumed to be periodically triggered and the different tasks communicate by unidirectional buffers. The problem we cope with is how to effectively share the resources so that some specified Quality of Service (QoS) requirements ar... View full abstract»

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  • 7 Great Reasons for Joining the IEEE Computer Society [advertisement]

    Publication Year: 2010, Page(s): 431
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  • Silver Bullet Security Podcast series

    Publication Year: 2010, Page(s): 432
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  • TC Information for authors

    Publication Year: 2010, Page(s): c3
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  • [Back cover]

    Publication Year: 2010, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org