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IEEE Design & Test of Computers

Issue 6 • Dec. 1988

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Displaying Results 1 - 6 of 6
  • Evolution of the electronic design automation industry

    Publication Year: 1988, Page(s):8 - 13
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (426 KB)

    The author discusses the last 25 years of the evolution of electronic design automation (EDA). He first examines the industry's dynamics and describes how it has coped with the increasing complexity of circuits. He argues that survival in the electronic design automation industry depends on how well it can produce a sequence of properly planned follow-on products and addresses the evolution of the... View full abstract»

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  • Design automation systems in Japan

    Publication Year: 1988, Page(s):14 - 21
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (703 KB)

    A brief historical overview is given of computer-aided design of integrated circuits. Layout strategies are examined, with emphasis on the hierarchical approach, which is the one most commonly adopted for semicustom LSIs. Functional and logic design are discussed, covering languages, logic synthesis, and hardware. A design example is presented to illustrate the use of the advanced tools discussed.... View full abstract»

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  • Automated BIST for sequential logic synthesis

    Publication Year: 1988, Page(s):22 - 32
    Cited by:  Papers (40)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (839 KB)

    An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. ... View full abstract»

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  • Incremental switch-level analysis

    Publication Year: 1988, Page(s):33 - 42
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    An algorithm is presented for extracting a two-level subnetwork hierarchy from flat netlists. They discuss the application of this algorithm to incremental circuit analysis in the Cosmos compiled switch-level simulator. The algorithm decreases the network preprocessing time for Cosmos by nearly an order of magnitude. The file system is used as a large hash table that retains information over many ... View full abstract»

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  • PROUD: a sea-of-gates placement algorithm

    Publication Year: 1988, Page(s):44 - 56
    Cited by:  Papers (77)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (923 KB)

    An efficient method is proposed for placing modules in large and highly complex sea-of-gates chips that include preplaced I/O pads and macrocells. PROUD repeatedly solves sparse linear equations. A resistive network analogy of the placement problem and convexity of the objective function are key concepts in this algorithm. The algorithm was tested on nine real circuits. For a triple-metal-layer, 1... View full abstract»

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  • The reliability of approximate testability measures

    Publication Year: 1988, Page(s):57 - 67
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (777 KB)

    Techniques for gauging the accuracy of approximate testability measures that estimate the random-pattern testability of gate-level faults in designs with combinational logic are considered. The measures examined are overall fault-exposure distribution, high coverage, and fault grading. Sampling techniques are compared with the Stafan and Protest approximate testability measures. For random-pattern... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty