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IEEE Design & Test of Computers

Issue 1 • Jan.-Feb. 2008

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Displaying Results 1 - 25 of 28
  • [Front cover]

    Publication Year: 2008, Page(s): c1
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  • [Advertisements]

    Publication Year: 2008, Page(s): c2
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  • IEEE Design & Test Call for Papers

    Publication Year: 2008, Page(s): 1
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  • Table of contents

    Publication Year: 2008, Page(s):2 - 3
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  • From the EIC

    Publication Year: 2008, Page(s): 4
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  • [Masthead]

    Publication Year: 2008, Page(s): 5
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  • Guest Editors' Introduction: The Evolution of RFIC Design and Test

    Publication Year: 2008, Page(s):6 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    There are several challenges facing RFIC design and test. The demand in the wireless market will drive RFIC products. For RFIC chipsets, improvements are needed for the elimination of passive components, better integrated passives, power reduction, modeling of devices and interconnects, packaging, and cost-effective testing. However, this innovation cannot come at the cost of time to market for ne... View full abstract»

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  • Build Your Career [advertisement]

    Publication Year: 2008, Page(s): 9
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  • Design and Analysis of a Transversal Filter RFIC in SiGe Technology

    Publication Year: 2008, Page(s):10 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB) | HTML iconHTML

    Filters are a critical component of every high-speed data communications system. Die area, power consumption, and RFIC integration are primary concerns for filter designers. The authors of this article have designed and fabricated a low-power analog filter with greatly reduced die area compared to passive delay lines. This transversal filter design has been realized in 47-GHz SiGe process technolo... View full abstract»

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  • Advertiser Index

    Publication Year: 2008, Page(s): 17
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  • Design of a Low-Noise UWB Transceiver SiP

    Publication Year: 2008, Page(s):18 - 28
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (959 KB) | HTML iconHTML

    Ultrawideband (UWB) wireless communication systems are emerging as a promising solution for high-data-rate and short-distance wireless data transmission. In this article, we introduce a low-noise UWB transceiver SiP design for a compact implementation in a small mobile platform. The SiP's transmitter chip has a fully digital circuit implementation with a passive band-pass filter to meet a US Feder... View full abstract»

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  • Decreasing Test Qualification Time in AMS and RF Systems

    Publication Year: 2008, Page(s):29 - 37
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB) | HTML iconHTML

    The authors of this article illustrate a means to use design models and simulation testbenches to decrease manufacturing test costs. This technique enables test cost optimization early in the RFIC design phase. In this article, we propose a test set optimization and qualification method that targets test application time, cost, and quality while also decreasing the generation time of production te... View full abstract»

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  • Light-Enhanced FET Switch Improves ATE RF Power Settling

    Publication Year: 2008, Page(s):38 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (558 KB) | HTML iconHTML

    RFIC testing requires cost-effective and innovative hardware implementation. The authors of this article have dramatically improved the speed of RF switches on high-performance ATE by shining a bright light on the switches. This solution provides practical, cost-effective RF testing. View full abstract»

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  • Time-Division-Multiplexed Test Delivery for NoC Systems

    Publication Year: 2008, Page(s):44 - 51
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (823 KB) | HTML iconHTML

    This test-scheduling approach for NoC designs minimizes test time through high-speed test delivery over the network, with test data interleaved via time-division multiplexing (TDM), and through slower test execution at the target cores. Results with a test-scheduling algorithm and a simulated test case from ITC 2002 SoC benchmarks show significant test time and I/O savings compared to a single-clo... View full abstract»

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  • Low-Impact Processor for Dynamic Runtime Power Management

    Publication Year: 2008, Page(s):52 - 62
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1198 KB) | HTML iconHTML

    This article presents a method of modifying a processor so that it can estimate its own power and energy consumption in parallel with application execution. The authors have applied the method to an existing 32-bit processor and demonstrated it on a range of benchmarks. The system adds only a small increase in average power consumption and chip area. View full abstract»

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  • IEEE Computer Society Digital Library Advertisement

    Publication Year: 2008, Page(s): 63
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  • Hybrid-SBST Methodology for Efficient Testing of Processor Cores

    Publication Year: 2008, Page(s):64 - 75
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (586 KB) | HTML iconHTML

    In this article, we introduce a hybrid-SBST methodology for efficient testing of commercial processor cores that effectively uses the advantages of various SBST methodologies. Self-test programs based on deterministic structural SBST methodologies combined with verification-based self-test code development and directed RTPG constitute a very effective H-SBST test strategy. The proposed methodology... View full abstract»

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  • Simultaneous Switching Noise: The Relation between Bus Layout and Coding

    Publication Year: 2008, Page(s):76 - 86
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (830 KB) | HTML iconHTML

    As device geometries shrink and power supply voltages decrease, simultaneous switching noise has increasingly detrimental effects on IC reliability. The authors investigate the worst-case conditions for SSN generated by a single switching wire and analyze the impact of transition-reducing encoding on SSN. They show that switching-pattern and layout considerations have a significant impact on TRE p... View full abstract»

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  • Distributed Systems Online [advertisement]

    Publication Year: 2008, Page(s): 87
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  • In Conversation with Tensilica CEO Chris Rowen

    Publication Year: 2008, Page(s):88 - 95
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (314 KB) | HTML iconHTML

    IEEE Design & Test's Ken Wagner interviews Chris Rowen—founder, president, and CEO of Tensilica. Rowen has come to prominence in the past few years as having founded and developed a successful soft-core processor company. Tensilica specializes in efficiently programmable embedded microprocessors with integrated tool chains. In this interview, Rowen discusses the history of MIPS Com... View full abstract»

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  • How to make your own processor architecture (review of Processor Design: System-on-Chip Computing for ASICs and FPGAs by Nurmi, J., Ed.; 2007) [Book reviews]

    Publication Year: 2008, Page(s):96 - 98
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  • IEEE Pervasive Computing [advertisement]

    Publication Year: 2008, Page(s): 99
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  • CEDA Currents

    Publication Year: 2008, Page(s):100 - 101
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  • DATC Newsletter

    Publication Year: 2008, Page(s): 102
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  • TTTC Newsletter

    Publication Year: 2008, Page(s): 103
    Cited by:  Papers (1)
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty