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IEEE Design & Test of Computers

Issue 6 • June 2006

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  • [Front cover]

    Publication Year: 2006, Page(s): c1
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  • Table of contents

    Publication Year: 2006, Page(s): c2
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  • Handling variations and uncertainties

    Publication Year: 2006, Page(s): 434
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  • Masthead

    Publication Year: 2006, Page(s): 435
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  • Guest Editors' Introduction: Process Variation and Stochastic Design and Test

    Publication Year: 2006, Page(s):436 - 437
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (62 KB) | HTML iconHTML

    As silicon manufacturing processes scale to and beyond the 65-nm node, process variations are consuming an increasingly larger portion of design and test budgets. Such variations play a significant part in subthreshold leakage and other important device performance metrics. The rise in inherent systematic and random nonuniformity as we scale our silicon devices to the level of atomic scaling will ... View full abstract»

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  • Testing On-Die Process Variation in Nanometer VLSI

    Publication Year: 2006, Page(s):438 - 451
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    Ring oscillators are not new, but the authors of this article use them in a novel, unconventional way to monitor process variation at different regions of a die in the frequency domain. Measuring the variation of each design or fabrication parameter is infeasible from a circuit designer's perspective. Therefore, we propose a methodology that approaches PV from a test perspective. This methodology ... View full abstract»

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  • Statistical Test Compaction Using Binary Decision Trees

    Publication Year: 2006, Page(s):452 - 462
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB) | HTML iconHTML

    In this work, we use binary decision trees (BDTs) for statistical test compaction, because they have the following properties. First, decision trees require no assumption on the type of correlation (if any) that exists between Tred and Tkept. This makes it possible to derive a more accurate representation of Fi(Tkept) from the collected test data. Also, ... View full abstract»

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  • Call for Papers

    Publication Year: 2006, Page(s): 463
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  • A DFT Approach for Testing Embedded Systems Using DC Sensors

    Publication Year: 2006, Page(s):464 - 475
    Cited by:  Papers (16)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB) | HTML iconHTML

    In this article, we propose a sensor-based BIT scheme. By using sensors, we mitigate any issues related to signal integrity and diversity in the test response capture process. Also, BIT can provide a test framework to estimate specifications during production testing for various modules in a heterogeneous SoC or SiP. This scheme involves designing sensors for each module directly into the device u... View full abstract»

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  • Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design

    Publication Year: 2006, Page(s):476 - 483
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1246 KB) | HTML iconHTML

    This case study discusses how to use adaptive circuits in a big dual-core microprocessor to combat process variation. The large die size also makes it suffer more on-die process variation. To prevent continuous design updates or multiple design optimizations, designs incorporate adaptive techniques that achieve the highest performance possible. Although adaptive techniques are not new, having been... View full abstract»

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  • ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon

    Publication Year: 2006, Page(s):484 - 490
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    ElastIC must deal with extremes a multiple core processor subjected to huge process variations, transistor degradations at varying rates, and device failures. In this article, we present a broad vision of a new cohesive architecture, ElastIC, which can provide a pathway to successful design in unpredictable silicon. ElastIC is based on aggressive run-time self-diagnosis, adaptivity, and self-heali... View full abstract»

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  • Call for Papers

    Publication Year: 2006, Page(s): 491
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  • An Exciting Time in Engineering

    Publication Year: 2006, Page(s):492 - 499
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  • Book Reviews: NoC, NoC ... Who's there?

    Publication Year: 2006, Page(s):500 - 501
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  • Design and test on chip for EMC

    Publication Year: 2006, Page(s):502 - 503
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  • East-West Design & Test Workshop

    Publication Year: 2006, Page(s):504 - 505
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  • CEDA Currents

    Publication Year: 2006, Page(s): 506
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  • TTTC Newsletter

    Publication Year: 2006, Page(s): 507
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  • DATC Newsletter

    Publication Year: 2006, Page(s): 508
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  • IEEE Computer Society Information

    Publication Year: 2006, Page(s): 509
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  • IEEE Design & Test of Computers 2006 Annual Index, Volume 23

    Publication Year: 2006, Page(s):510 - 519
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  • Tackling variability and reliability challenges

    Publication Year: 2006, Page(s): 520
    Cited by:  Papers (13)  |  Patents (1)
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  • [Back inside cover]

    Publication Year: 2006, Page(s): c3
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  • [Back cover]

    Publication Year: 2006, Page(s): c4
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty