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IEE Proceedings E - Computers and Digital Techniques

Issue 3 • May 1992

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Displaying Results 1 - 15 of 15
  • Implementation issues of sigmoid function and its derivative for VLSI digital neural networks

    Publication Year: 1992, Page(s):207 - 214
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (492 KB)

    Proposes a number of different implementations for the first derivative of the sigmoid function. The implementation of the sigmoid function employs a powers-of-two piecewise linear approximation. The best implementation scheme for the derivative is suggested based on overall speed performance (circuit speed and training time) and hardware requirements. View full abstract»

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  • Highly parallel representations for linear maps

    Publication Year: 1992, Page(s):173 - 178
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (320 KB)

    A class of computationally-fast linear (CFL) transformations described have particularly efficient implementations in dedicated arrays with a small local memory. Using the least squares approximation technique, the paper develops an optimal orthogonal decomposition of arbitrary linear transformations in terms of these new CFL maps. The representation has a natural realisation in terms of parallel ... View full abstract»

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  • Cryptographic master-key-generation scheme and its application to public key distribution

    Publication Year: 1992, Page(s):203 - 206
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (304 KB)

    Presents a cryptographic master-key-generation scheme based on a recently developed cryptographic multi-level key generation scheme. That multilevel key generation scheme is a logical complement to the well known Akl-Taylor-MacKinnon-Meijer scheme, and is particularly efficient for hierarchical structures of limited depth, which is the case for the master-key application at hand. The master-key pr... View full abstract»

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  • Design of a high-performance IIR digital filter chip

    Publication Year: 1992, Page(s):195 - 202
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (592 KB)

    The design of a novel high-performance IIR digital filter chip is presented. The chip has been implemented using 1.5 mu m double-layer metal CMOS technology. The filter chip operates on an 11-bit two's-complement input data, a 12-bit two's-complement coefficient word and produces a two's-complement 14-bit output. The main component of the chip is a fine grained systolic array architecture that int... View full abstract»

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  • Realisation of pipelined mesh algorithms on hypercubes

    Publication Year: 1992, Page(s):189 - 194
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (356 KB)

    Presents efficient techniques for realisation of pipelined mesh algorithms on hypercubes. A mesh algorithm is an algorithm inherently suited to a mesh-connected iterative logic array. Previous treatment of the subject by other researchers was concerned mostly with the embedding of a mesh on a hypercube which must be big enough to host all the mesh points. The authors consider a more practical situ... View full abstract»

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  • Computation of 2-dimensional fast transforms and image filtering on transputer networks

    Publication Year: 1992, Page(s):249 - 261
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (896 KB)

    The computation of 2-dimensional fast Fourier and cas-cas transforms and image filtering via transform-domain block convolution on transputer networks is discussed. Loosely coupled message-passing architectures require a fairly course-grained algorithmic decomposition. They are therefore in general only suited for multidimensional transforms. The paper considers computation of two-dimensional tran... View full abstract»

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  • Performance evaluation of communicating sequential processes (CSP) using Petri nets

    Publication Year: 1992, Page(s):237 - 241
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (308 KB)

    CSP has become a standard model for programming languages using synchronised communication. Performance evaluation of CSP modelled by Petri nets is investigated in the paper. The command execution time is expressed by non-negative real numbers. Relationships among frequences of executing the commands are described by a vector with natural components. The model is useful in real-time systems design... View full abstract»

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  • Performance analysis of slotted rings with finite buffers

    Publication Year: 1992, Page(s):215 - 220
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (360 KB)

    Many modelling studies have been conducted on a slotted ring with station buffers which are assumed to be either one or infinity. In reality, stations have finite buffers and arriving packets are rejected at a full buffer. The paper studies the behaviour of a slotted ring with finite buffering capability using a two-dimensional discrete time Markov chain. The characteristics of the single station ... View full abstract»

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  • Systolic arrays: how to choose them

    Publication Year: 1992, Page(s):179 - 188
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (624 KB)

    Looks closely into the effect of objective function optimisation on the architecture of systolic arrays. Various objective functions such as area, speed, throughput, AT and AT2 have been considered. In each case, when the objective function is optimised, a different systolic array is produced. The authors present their approach systematically using the space-time techniques of mapping a... View full abstract»

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  • On the reduction of the programming cost of soft switches for reconfigurable two-dimensional arrays

    Publication Year: 1992, Page(s):262 - 268
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (556 KB)

    Methods for reducing the cost involved in the programming of nonpermanent (soft) switching elements in an augmented interconnection network for reconfigurable two-dimensional arrays are considered. The proposed approach is based on an optimised execution of the disjoint tree programming technique proposed by Boubekeur et al. Reduction in cost is analysed with respect to either the sequential or pa... View full abstract»

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  • Simple two-stage method for the accurate location of Hough transform peaks

    Publication Year: 1992, Page(s):242 - 248
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (728 KB)

    The paper describes a method for the rapid, accurate location of Hough transform peaks. First, it is recognised that votes may be rather sparsely distributed in parameter space, so a reliable means of clustering them is vital. Although this may be achieved by multiresolution techniques, an important consideration is that peaks are generally noisy and may be multimodal, so care must be taken over a... View full abstract»

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  • Performance of a RISC machine with two level caches

    Publication Year: 1992, Page(s):221 - 229
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (584 KB)

    To improve computer system performance, small high-speed memories (caches) often accompany CPU complexes. With the advancement of VLSI densities, two levels of cache are becoming more common. The authors evaluate the performance of a computer with a two level cache using simulation techniques. The address stream that drives the simulator is gathered from an experimental RISC processor running a re... View full abstract»

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  • Real-time simulation of videophone image coding algorithms on reconfigurable multicomputers

    Publication Year: 1992, Page(s):269 - 279
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (848 KB)

    The simulation at bit stream level of motion video image coding algorithms provides an effective means of algorithm development and evaluation. The paper describes the problems encountered in using a large reconfigurable transputer-based multicomputer to simulate, in real-time, realistically complex videophone image coding algorithms. A primary aim was to enable the output of all stages of the alg... View full abstract»

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  • Division and bit-serial multiplication over GF(qm)

    Publication Year: 1992, Page(s):230 - 236
    Cited by:  Papers (22)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (392 KB)

    Division and bit-serial multiplication in finite fields are considered. Using co-ordinates of the supporting elements it is shown that, when field elements are represented by polynomials, division over GF(qm) can be performed by solving a system of m linear equations over GF(q). For a canonical basis representation, a relationship between the division and the discrete-time Wiener-Hopf e... View full abstract»

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  • KBIF: a frame system capable of performing inexact reasoning involving various inexactness factors

    Publication Year: 1992, Page(s):280 - 292
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1016 KB)

    KBIF, a frame system capable of representing inexact knowledge of different significance and performing weighted, inexact reasoning and temporal projection is described. Important features of KBIF facilitate inexact reasoning; namely weights are associated with slots in accordance with their relative importance to a frame, confidence factors are associated with slot values to denote their confiden... View full abstract»

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