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IEEE Transactions on Computers

Issue 6 • June 1984

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1984, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1984, Page(s): c2
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  • Foreword—liable and Fault-Tolerant Computing

    Publication Year: 1984, Page(s):465 - 466
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1515 KB)

    THIS issue of the IEEE TRANSACTIONS ON COMPUTERS continues a series of Special Issues on fault-tolerant computing that began in 1971. Since that time, concern for high reliability and fault tolerance has moved from such specialized application areas as telephone switching and spacecraft control into the general commercial computer market. Developments in VLSI technology, especially the microproces... View full abstract»

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  • On Random Pattern Test Length

    Publication Year: 1984, Page(s):467 - 474
    Cited by:  Papers (149)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1462 KB)

    The testing of large logic networks with random patterns is examined. Work by previous workers for single faults is extended to a class of multiple fault situations. Not only is the problem of fault detection in the presence of nonmasking multiple faults treated, but the question of distinguishing between them is also examined. It is shown that a test that merely exposes each fault has a high prob... View full abstract»

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  • Functional Testing of Microprocessors

    Publication Year: 1984, Page(s):475 - 485
    Cited by:  Papers (112)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3715 KB)

    This paper presents a new and systematic method to generate tests for microprocessors. A functional level model for the microprocessor is used and it is represented by a reduced graph. A new and comprehensive model of the instruction execution process is developed. Various types of faults are analyzed and it is shown that with the use of appropriate codewords all faults can be classified into thre... View full abstract»

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  • An 0(n2.5) Fault Identification Algorithm for Diagnosable Systems

    Publication Year: 1984, Page(s):486 - 492
    Cited by:  Papers (168)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2784 KB)

    Consider a system composed of n independent processors, each of which tests a subset of the others. It is assumed that at most tp of these processors are permanently faulty and that the outcome of a test is reliable if and only if the processor which performed the test is fault free. Such a system is said to be tp-diagnosable if, given any complete collection of test results, the set of faulty pro... View full abstract»

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  • Design and Application of Self-Testing Comparators Implemented with MOS PLA's

    Publication Year: 1984, Page(s):493 - 506
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4344 KB)

    A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules... View full abstract»

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  • The Role of a Maintenance Processor for a General-Purpose Computer System

    Publication Year: 1984, Page(s):507 - 517
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3643 KB)

    Research and development in fault-tolerant computing has shown that a dedicated processor, called a maintenance processor, can efficiently monitor, control, and maintain the operation of its host computer. This paper presents the general system structure and common functional capabilities of the maintenance processor, and illustrates its utilization with a survey of actual implementations availabl... View full abstract»

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  • Algorithm-Based Fault Tolerance for Matrix Operations

    Publication Year: 1984, Page(s):518 - 528
    Cited by:  Papers (513)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3363 KB)

    The rapid progress in VLSI technology has reduced the cost of hardware, allowing multiple copies of low-cost processors to provide a large amount of computational capability for a small cost. In addition to achieving high performance, high reliability is also important to ensure that the results of long computations are valid. This paper proposes a novel system-level method of achieving high relia... View full abstract»

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  • Error Detection Process—Model, Design, and Its Impact on Computer Performance

    Publication Year: 1984, Page(s):529 - 540
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2265 KB)

    Conventionally, reliability analyses either assume that a fault/error is detected immediately as it occurs, or ignore damage caused by imperfect detection mechanisms and error latency, namely, the time interval between the occurrence of an error and the detection of that error. View full abstract»

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  • Verification Testing—A Pseudoexhaustive Test Technique

    Publication Year: 1984, Page(s):541 - 546
    Cited by:  Papers (145)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present day automatic test pattern generation (ATPG) programs. Fault simulation or fault modeling is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher—all irredundant multiple as... View full abstract»

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  • Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs

    Publication Year: 1984, Page(s):546 - 550
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1185 KB)

    Two new general designs for totally self-checking (TSC) comparators with an arbitrary number of input vectors are presented. The multipattern comparator combines modified TSC 2-input comparators and a TSC two-rail checker that requires only four patterns for self-testing. The counter-driven comparator adds circuitry to generate an exhaustive set of test patterns. The designs are compared on the ba... View full abstract»

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  • A Performability Solution Method for Degradable Nonrepairable Systems

    Publication Year: 1984, Page(s):550 - 554
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1190 KB)

    An algorithm is developed for solving a broad class of performability models wherein system performance is identified with "reward." More precisely, for a system S and a utilization period T, the performance variable of the model is the reward derived from using S during T. The state behavior of S is represented by a finite-state stochastic process (the base model); reward is determined by reward ... View full abstract»

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  • The Design of Easily Testable VLSI Array Multipliers

    Publication Year: 1984, Page(s):554 - 560
    Cited by:  Papers (64)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1461 KB)

    Array multipliers are well suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are difficult to test. This correspondence shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called C-testable if all its adder cells can be exhaustively tested while requiring only... View full abstract»

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  • Built-In Testing of One-Dimensional Unilateral Iterative Arrays

    Publication Year: 1984, Page(s):560 - 564
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1197 KB)

    It has been shown in the literature that C-testable iterative arrays have very simple test structures, independent of the length of the arrays. We show in this work that all C-testable arrays are also pI-testable, which is a property yielding, in many cases, rather simple built-in-testing structures, both for the test generator and for the response verifier. View full abstract»

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  • A Study of Software Failures and Recovery in the MVS Operating System

    Publication Year: 1984, Page(s):564 - 568
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1154 KB)

    This paper describes an analysis of system detected software errors on the MVS operating system at the Center for Information Technology (CIT), Stanford University. The analysis procedure demonstrates a methodology by which systems with automatic recovery features can be evaluated. Most common error categories are determined and related to the program in execution at the time of the error. The sev... View full abstract»

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  • Fault Tolerance in Binary Tree Architectures

    Publication Year: 1984, Page(s):568 - 572
    Cited by:  Papers (87)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1149 KB)

    Binary tree network architectures are applicable in the design of hierarchical computing systems and in specialized high-performance computers. In this correspondence, the reliability and fault tolerance issues in binary tree architecture with spares are considered. Two different fault-tolerance mechanisms are described and studied, namely: 1) scheme with spares; and 2) scheme with performance deg... View full abstract»

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  • Modified Berger Codes for Detection of Unidirectional Errors

    Publication Year: 1984, Page(s):572 - 575
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (803 KB)

    Modified Berger codes are defined in this correspondence. They are less expensive than the ordinary Berger codes in terms of the number of check bits and the cost of checkers. As a tradeoff, their error detection ability is slightly lower, although these codes can detect most unidirectional errors. View full abstract»

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  • Unidirectional Error Codes for Shift-Register Memories

    Publication Year: 1984, Page(s):575 - 578
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (850 KB)

    In this correspondence we give an efficient error control technique for mass memories such as magnetic bubble memories, magnetic tapes, etc. The code discussed here is a modification of the cyclic redundancy check (CRC) used in magnetic tape units. An arithmetic redundancy check (ARC) with respect to an appropriate modulus (or check base) replaces the CRC, and the result is a systematic code which... View full abstract»

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  • A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing

    Publication Year: 1984, Page(s):578 - 583
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1151 KB)

    This correspondence demonstrates a new kind of error-checking scheme for multioutput combinational circuits and its use for a built-in testing method. In the error-checking logic employed, the output from the circuits being checked is partitioned into several groups. The predicted group parity is compared to that produced from the output in each group. This checking circuit, called a group-parity ... View full abstract»

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  • PLA Implementation of k-out-of-n Code TSC Checker

    Publication Year: 1984, Page(s):583 - 588
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1124 KB)

    PLA implementations of totally self-checking (TSC) checkers for k-out-of-n codes, where 2 ≤k ≤ n -2, are presented. For k-out-of-2k, k-out-of-2k + 1, k + 1-out-of-2k + 1, and k ± 1-out-of-2k codes, TSC checkers are designed using only one PLA. TSC checkers for all other codes are designed using 2 PLA's, and in fact the second PLA is very small for most of the codes. View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): 588
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1984, Page(s): 588
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org