By Topic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 3 • March 2006

Filter Results

Displaying Results 1 - 22 of 22
  • Table of contents

    Publication Year: 2006, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (48 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2006, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (38 KB)
    Freely Available from IEEE
  • Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm

    Publication Year: 2006, Page(s):389 - 402
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (992 KB) | HTML iconHTML

    This paper addresses the problem of identifying the minimum pipelining needed in an asynchronous circuit (e.g., number/size of pipeline stages/latches required) to satisfy a given performance constraint, thereby implicitly minimizing area and power for a given performance. The paper first shows that the basic pipeline optimization problem for asynchronous circuits is NP-complete. Then, it presents... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Verification of timed circuits with failure-directed abstractions

    Publication Year: 2006, Page(s):403 - 412
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    This paper presents a method to address state explosion in timed-circuit verification by using abstraction directed by the failure model. This method allows us to decompose the verification problem into a set of subproblems, each of which proves that a specific failure condition does not occur. To each subproblem, abstraction is applied using safe transformations to reduce the complexity of verifi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique

    Publication Year: 2006, Page(s):413 - 422
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED) technique. In REcomputing with Shifted Operands (RESO), operations (additions, subtractions, etc.) are carried out twice-once on the basic input and once on the shifted input. Results from these two operations are compared... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Active leakage power optimization for FPGAs

    Publication Year: 2006, Page(s):423 - 437
    Cited by:  Papers (52)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB) | HTML iconHTML

    Active leakage power dissipation is considered in field-programmable gate arrays (FPGAs) and two "no cost" approaches for active leakage reduction are presented. It is well known that the leakage power consumed by a digital CMOS circuit depends strongly on the state of its inputs. The authors' first leakage reduction technique leverages a fundamental property of basic FPGA logic elements [look-up ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic voltage scaling of mixed task sets in priority-driven systems

    Publication Year: 2006, Page(s):438 - 453
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB) | HTML iconHTML

    This paper describes dynamic voltage scaling (DVS) algorithms for real-time systems with both periodic and aperiodic tasks. Although many DVS algorithms have been developed for real-time systems with periodic tasks, none of them can be used for a system with both periodic and aperiodic tasks because of the arbitrary temporal behaviors of aperiodic tasks. This paper proposes off-line and on-line DV... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An automated and efficient substrate noise analysis tool

    Publication Year: 2006, Page(s):454 - 468
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB) | HTML iconHTML

    This paper presents a methodology for the efficient modeling of substrate noise coupling. A closed-form Green's function for nonuniformly doped substrates is employed with the correct singular characteristics. A novel global surface impedance matrix scheme is introduced to efficiently model nonuniformly doped wells, channel stop implants, and buried layers. Layout, device, and netlist extractors a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance analysis of latency-insensitive systems

    Publication Year: 2006, Page(s):469 - 483
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    This paper formally models and studies latency-insensitive systems (LISs) through max-plus algebra. We introduce state traces to model behaviors of LISs and obtain a formally proved performance upper bound achievable by latency-insensitive design. An implementation of the latency-insensitive protocol that can provide robust communication through back-pressure is also proposed. The intrinsic perfor... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An O(bn2) time algorithm for optimal buffer insertion with b buffer types

    Publication Year: 2006, Page(s):484 - 489
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    Buffer insertion is a popular technique to reduce the interconnect delay. The classic buffer insertion algorithm of van Ginneken has a time complexity of O(n2), where n is the number of buffer positions. Lillis, Cheng, and Lin extended van Ginneken's algorithm to allow b buffer types in O(b2n2) time. For modern design libraries that contain hundreds of buffers, it ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algorithmic study of single-layer bus routing for high-speed boards

    Publication Year: 2006, Page(s):490 - 503
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1608 KB) | HTML iconHTML

    As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools cannot successfully handle these constraints any more. In this paper, the authors focus on the high-performance single-layer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization

    Publication Year: 2006, Page(s):504 - 517
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB) | HTML iconHTML

    In this paper, we present a family of multiobjective hypergraph-partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both the cut and the maximum subdomain degree are simultaneously minimized. This type of partitionings are critical for existing and emerging applications in very large scale integration (VLSI) computer-aided design (CAD) as the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • PipeRoute: a pipelining-aware router for reconfigurable architectures

    Publication Year: 2006, Page(s):518 - 532
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    We present a pipelining-aware router for fieldprogrammable gate arrays (FPGAs). The problem of routing pipelined signals is different from the conventional FPGA routing problem. The two-terminal ND pipelined routing problem is to find the lowest cost route between a source and sink that goes through at least N (N≥1) distinct pipelining resources. In the case of a multiterminal pipeli... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New and improved BIST diagnosis methods from combinatorial Group testing theory

    Publication Year: 2006, Page(s):533 - 543
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    We examine the general problem of built-in-self-test (BIST) diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vectors, faulty scan cells, and faulty items. We develop an abstract model of this problem and show a fundamental correspondence to the well-established subject of combinatorial group testing (CGT) (D. Du and F. K.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Satisfiability-based test generation for nonseparable RTL controller-datapath circuits

    Publication Year: 2006, Page(s):544 - 557
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    In this paper, we present a satisfiability (SAT)-based algorithm for automatically generating test sequences that target gate-level stuck-at faults in a circuit by using its register-transfer level (RTL) description. Our methodology uses a unified RTL circuit representation, called assignment-decision diagrams (ADDs), for test analysis. Test generation proceeds by abstracting the components in thi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis and methodology for multiple-fault diagnosis

    Publication Year: 2006, Page(s):558 - 575
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB) | HTML iconHTML

    In this paper, we propose a multiple-fault-diagnosis methodology based on the analysis of failing patterns and the structure of diagnosed circuits. We do not consider the multiple-fault behavior explicitly, but rather partition the failing outputs and use an incremental simulation-based technique to diagnose failures one at a time. Our methodology can be further improved by selecting appropriate d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-level delay test generation for modular circuits

    Publication Year: 2006, Page(s):576 - 590
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB) | HTML iconHTML

    Circuits containing functional blocks (modules) whose implementation details are not available pose major problems for delay fault testing. High-level testing methods are needed, but they often generate excessively large test sets to ensure good realization-independent fault coverage. This paper extends high-level delay fault models to large modular logic circuits by demonstrating that a hierarchi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Scan-BIST based on transition probabilities for circuits with single and multiple scan chains

    Publication Year: 2006, Page(s):591 - 596
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    It is demonstrated that it is possible to generate a deterministic test set that detects all the detectable single stuck-at faults in a full-scan circuit such that each test vector contains a small number of transitions from 0 to 1 or from 1 to 0 when considering consecutive input values. Using this result, it is shown that built-in test-pattern generation for scan circuits can be based on transit... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-level synthesis of ΔΣ Modulator topologies optimized for complexity, sensitivity, and power consumption

    Publication Year: 2006, Page(s):597 - 607
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB) | HTML iconHTML

    This paper proposes a novel topology-synthesis methodology for single-loop single-bit ΔΣ modulators. The goal is to explore all possible topologies and to obtain the optimal topology under various design considerations, such as hardware complexity, modulator sensitivity, and power consumption. A generic modulator architecture that incorporates all possible feedback and feedforward sign... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 2006 IEEE International Symposium on Circuits and Systems (ISCAS 2006)

    Publication Year: 2006, Page(s): 608
    Request permission for commercial reuse | PDF file iconPDF (504 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2006, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (27 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2006, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (23 KB)
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu