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IEEE Design & Test of Computers

Issue 6 • Nov.-Dec. 2005

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  • [Front cover]

    Publication Year: 2005, Page(s): c1
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  • Table of contents

    Publication Year: 2005, Page(s):490 - 491
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  • Masthead

    Publication Year: 2005, Page(s): 492
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  • Going 3D: Silicon and D&T

    Publication Year: 2005, Page(s):493 - 494
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    3D integration techniques, from wafer stacking to transistors along trench walls in 3D circuits, have existed since the 1980s. Recently, however, new products and platforms—enabled by substantial increases in processing, communications, and storage--have driven major advances in this area. This issue explores the recent advances in 3D integration and discusses the accompanying challenges. The... View full abstract»

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  • Guest Editors' Introduction: New Dimensions in 3D Integration

    Publication Year: 2005, Page(s):496 - 497
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB) | HTML iconHTML

    Although various forms of 3D fabrication technology have existed for a few decades, only in recent years have researchers developed highly integrated 3D design technologies that are potentially manufacturable and economically feasible. Several companies are already marketing 3D structures built by wafer stacking, where the distance between the 3D layers on a wafer are on the order of the wafer thi... View full abstract»

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  • Demystifying 3D ICs: the pros and cons of going vertical

    Publication Year: 2005, Page(s):498 - 510
    Cited by:  Papers (357)  |  Patents (70)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (590 KB) | HTML iconHTML

    This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D techno... View full abstract»

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  • 3D chip stack technology using through-chip interconnects

    Publication Year: 2005, Page(s):512 - 518
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB) | HTML iconHTML

    The current technology in micro-and nano-electronics is insufficient to meet future demands for several applications. Most state-of-the-art solutions rely on so-called embedded technologies, which are both expensive and complex. One solution to the problem of integrating mixed technologies is the concept of 3D stacking. Our approach implements an epitaxial etch-stop layer for thickness control of ... View full abstract»

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  • Placement and routing in 3D integrated circuits

    Publication Year: 2005, Page(s):520 - 531
    Cited by:  Papers (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB) | HTML iconHTML

    Three-dimension technologies offer great promise in providing improvements in the overall circuit performance. Physical design plays a major role in the ability to exploit the flexibilities offered in the third dimension, and this article gives an overview of placement and routing methods for FPGA- and ASIC-style designs. We describe CAD techniques for placement and routing in 3D ICs, developed un... View full abstract»

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  • Physical design for 3D system on package

    Publication Year: 2005, Page(s):532 - 539
    Cited by:  Papers (31)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    The SoC paradigm is a system integration approach that integrates large numbers of transistors as well as various mixed-signal active and passive components onto a single chip. This realization-led to the 3D system-in-package (SiP) approach, alternatively called 3D ICs or 3D stacked die/package. Designers can take SiP a step further by embedding both active and passive components, but passive-comp... View full abstract»

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  • Predicting the performance of a 3D processor-memory chip stack

    Publication Year: 2005, Page(s):540 - 547
    Cited by:  Papers (22)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB) | HTML iconHTML

    We are exploring a 3D processor-memory stack for use with the message passing interface (MPI). The communication among processors in huge servers wastes several thousands of cycles. Most of these wasted cycles do not come from the communication link among the processors across the system, but rather in handling the message packets. A processor that could handle this message packing and communicati... View full abstract»

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  • First-order performance prediction of cache memory with wafer-level 3D integration

    Publication Year: 2005, Page(s):548 - 555
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB) | HTML iconHTML

    The advantages of 3D design can be exploited by reducing the memory access time. In this article, the authors use a simulator based on analytical models to build an optimal processor-memory configuration for two designs: a graphics processor and a microprocessor. One emerging alternative approach to relieving these interconnect constraints is the use of wafer-level 3D integration, which provides a... View full abstract»

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  • Bridging the processor-memory performance gap with 3D IC technology

    Publication Year: 2005, Page(s):556 - 564
    Cited by:  Papers (115)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    Microprocessor performance has been improving at roughly 60% per year. Memory access times, however, have improved by less than 10% per year. The resulting gap between logic and memory performance has forced microprocessor designs toward complex and power-hungry architectures that support out-of-order and speculative execution. Moreover, processors have been designed with increasingly large cache ... View full abstract»

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  • Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive

    Publication Year: 2005, Page(s): 565
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (43 KB) | HTML iconHTML

    The theme of the 2005 International Test Conference is “Test: Survival of the Fittest.” In conjunction with this year's ITC, this special section examines how test helps the fittest of the industry's chips, boards, and systems survive manufacturing to reach its customers. These articles discuss topics such as X-tolerant test response compaction, reducing yield loss using a constrained AT... View full abstract»

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  • X-tolerant test response compaction

    Publication Year: 2005, Page(s):566 - 574
    Cited by:  Papers (15)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to mini... View full abstract»

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  • A novel transition fault ATPG that reduces yield loss

    Publication Year: 2005, Page(s):576 - 584
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB) | HTML iconHTML

    In this article, we have presented a novel constrained broadside transition ATPG algorithm to avoid overtesting functionally (sequentially) untestable transition faults. In some circuits, significantly more functionally untestable transition faults were identified. At the same time, more faults could be detected without incidental detection of functionally untestable transition faults. With a test... View full abstract»

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  • IC outlier identification using multiple test metrics

    Publication Year: 2005, Page(s):586 - 595
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    With increasing variation in parametric data, it is necessary to adopt statistical means and correlations that consider other process parameters. Determining an appropriate threshold is difficult because of the several orders of magnitude variation in fault-free IDDQ. Therefore, it is necessary to use secondary information to identify outliers. This article proposed a combination of two... View full abstract»

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  • Designing "Vary" Good Circuitry

    Publication Year: 2005, Page(s):596 - 597
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  • Panel Summaries

    Publication Year: 2005, Page(s):598 - 599
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    An evening panel session entitled "Microelectronics and Test in 'The New Europe'--Challenges and Opportunities in Research and Industry," took place on 23 May at the 10th European Test Symposium (ETS 05). Raimund Ubar and Hans-Joachim Wunderlich (University of Stuttgart) organized the panel session, and Erik Jan Marinissen (Philips Research) served as moderator. Panelists included representatives ... View full abstract»

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  • 2005 IEEE East-West Design and Test Workshop

    Publication Year: 2005, Page(s): 600
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB) | HTML iconHTML

    The 3rd IEEE East-West Design and Test Workshop (EWDTW 2005) took place from 15 to 19 September in Odessa, Ukraine. The workshop's goal was for scientific schools and experts in Eastern and Western Europe (as well as other parts of the world) to exchange experiences in the design and test of electronic systems. Researchers from western countries presented an overview of design-and-test trends. And... View full abstract»

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  • Computer Society Information

    Publication Year: 2005, Page(s): 601
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  • Test Technology TC Newsletter

    Publication Year: 2005, Page(s):602 - 603
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  • IEEE Design & Test of Computers, 2005 Annual Index, Volume 22

    Publication Year: 2005, Page(s):604 - 615
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  • ITC is Cool

    Publication Year: 2005, Page(s): 616
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (44 KB) | HTML iconHTML

    ITC is cool. How can this be, you ask? This is the International Test Conference's 36th year, which makes it a middle-aged conference; and, as anyone who has ever been middle-aged knows, being cool at this time of life is a serious challenge. ITC doesn't try to be cool, at least not in the way that, say, Macworld does. ITC tries instead to be interesting, innovative, and informative. All three of ... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty