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IEEE Design & Test of Computers

Issue 3 • May-June 2003

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Displaying Results 1 - 18 of 18
  • A "powerful" issue!

    Publication Year: 2003, Page(s): 1
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  • Guest editors' introduction: on-chip power distribution networks

    Publication Year: 2003, Page(s):5 - 6
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  • Analysis and optimization of power grids

    Publication Year: 2003, Page(s):7 - 15
    Cited by:  Papers (22)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB) | HTML iconHTML

    As the complexity of power and ground networks increases, methods for efficient analysis and aggressive optimization of these networks become essential. Here, the authors describe efficient hierarchical methods for analyzing distribution networks. To optimize the networks, the authors call for techniques that reduce noise on the power grid, including topology selection, wire widening, and decoupli... View full abstract»

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  • Impact of low-impedance substrate on power supply integrity

    Publication Year: 2003, Page(s):16 - 22
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (697 KB) | HTML iconHTML

    Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometimes cause unforeseen problems. This article focuses especially on the relationship of the power delivery system to the silicon substrate properties, and shows how a low-impendance substrate can make a... View full abstract»

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  • Electrical modeling of integrated-package power and ground distributions

    Publication Year: 2003, Page(s):24 - 31
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (410 KB) | HTML iconHTML

    Ensuring reliable power distribution requires accurate modeling of on-package power and ground networks. This, in turn, necessitates efficient magnetic coupling modeling - a massively complex task. Extending their previous work, these authors introduce a window-based extraction technique that uses the physical concept of susceptance to control modeling complexity. View full abstract»

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  • Clock and power gating with timing closure

    Publication Year: 2003, Page(s):32 - 39
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB) | HTML iconHTML

    Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation. View full abstract»

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  • Microarchitectural dl/dt control

    Publication Year: 2003, Page(s):40 - 47
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (359 KB) | HTML iconHTML

    This article takes a high level of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through a set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation giving insight into the possible method to reduce such noise. View full abstract»

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  • Guest editor's introduction: advances in infrastructure IP

    Publication Year: 2003, Page(s): 49
    Cited by:  Papers (4)
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  • Online self-repair of FIR filters

    Publication Year: 2003, Page(s):50 - 57
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB) | HTML iconHTML

    Chip-level failure detection has been a target of research for some time, but today's very deep-submicron technology is forcing such research to move beyond detection. Repair, especially self-repair, has become very important for containing the susceptibility of today's chips. This article introduces a self-repair-solution for the digital FIR filter, one of the key blocks used in DSPs. View full abstract»

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  • Embedded-memory test and repair: infrastructure IP for SoC yield

    Publication Year: 2003, Page(s):58 - 66
    Cited by:  Papers (85)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (267 KB) | HTML iconHTML

    Today's complex SoCs need sophisticated infrastructure IP, not only to test and diagnose embedded memories but also to repair them and improve fabrication yield. The authors solution integrates memory IP with test and repair IP in a composite infrastructure IP that ensures manufacturing and field repair efficiency and optimizes SoC yield. View full abstract»

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  • Benefits of a SoC-specific test methodology

    Publication Year: 2003, Page(s):68 - 77
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    The tradeoff between IP protection and SoC-level test optimization has been an issue for some time. The more IP providers protect their IP, the less flexibility system developers have to control test costs and fault coverage. In this paper, a new approach dynamically extracts IP-related test information or optimizing SoC testing without jeopardizing IP protection. View full abstract»

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  • Infrastructure IP for configuration and test of boards and systems

    Publication Year: 2003, Page(s):78 - 87
    Cited by:  Papers (10)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (277 KB) | HTML iconHTML

    Embedding infrastructure IP to optimize chip-level manufacturing test and debugging has recently become common practice. However, adopting the same approach for boards and systems requires a different family of infrastructure IP. This article introduces such a family and discusses how it can optimize manufacturing test and debugging, as well as support configurability, especially in today's reconf... View full abstract»

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  • DAC Highlights

    Publication Year: 2003, Page(s):88 - 89
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  • DAC turns 40!

    Publication Year: 2003, Page(s):90 - 91
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  • DAC: serving the EDA community for 40 years

    Publication Year: 2003, Page(s):97 - 98
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  • DAC, Moore's Law still drive EDA

    Publication Year: 2003, Page(s):99 - 100
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  • CASS brings publishing to its DAC partnership

    Publication Year: 2003, Page(s):101 - 102
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  • First cadathlon programming contest held at 2002 ICCAD

    Publication Year: 2003, Page(s):104 - 107
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty