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IEEE Journal of Solid-State Circuits

Issue 6 • Dec. 1985

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Displaying Results 1 - 25 of 32
  • [Inside front cover - December 1985]

    Publication Year: 1985, Page(s): f2
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  • 1985 Index IEEE Journal of Solid-State Circuits Vol. SC-20

    Publication Year: 1985, Page(s):i1 - i17
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  • Table of contents (December 1985)

    Publication Year: 1985, Page(s):1081 - 1082
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  • Foreword (December 1985)

    Publication Year: 1985, Page(s):1083 - 1084
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  • An elliptic continuous-time CMOS filter with on-chip automatic tuning

    Publication Year: 1985, Page(s):1114 - 1121
    Cited by:  Papers (116)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (995 KB)

    A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the freq... View full abstract»

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  • A high-performance micropower switched-capacitor filter

    Publication Year: 1985, Page(s):1122 - 1132
    Cited by:  Papers (168)  |  Patents (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1393 KB)

    A description is given of a high-performance fifth-order low-pass switched-capacitor filter operating form a single 5-V supply. The filter uses a fully differential topology combined with input-to-output class AB amplifier design, dynamic biasing, and switched-capacitor common-mode feedback. An experimental prototype fabricated in a 5-/spl mu/m CMOS technology requires only 350 /spl mu/W of power ... View full abstract»

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  • A 500-MHz 8-bit D/A converter

    Publication Year: 1985, Page(s):1133 - 1137
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    An ultrafast monolithic 8-bit DAC is designed and fabricated. To realize this DAC, a new high-speed conversion technique, referred to as the data multiplexing method, and a variation of the segmented DAC (J.A. Shoeff, 1979) for low glitch are developed. The DAC is fabricated with shallow-groove-isolated 3-/spl mu/m VLSI technology with peak f/SUB T/'s of 4.5 GHz. An experimental 8-bit DAC features... View full abstract»

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  • An 8-MHz CMOS subranging 8-bit A/D converter

    Publication Year: 1985, Page(s):1138 - 1143
    Cited by:  Papers (69)  |  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1185 KB)

    A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/. View full abstract»

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  • A 20-V four-quadrant CMOS analog multiplier

    Publication Year: 1985, Page(s):1158 - 1168
    Cited by:  Papers (115)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1410 KB)

    A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the... View full abstract»

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  • A full duplex 1200/300 bit/s single-chip CMOS model

    Publication Year: 1985, Page(s):1169 - 1178
    Cited by:  Papers (1)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1423 KB)

    The design of a Bell 212A (AT&T) compatible single-chip modem is described, and measured results are presented. The IC(Fairchild /spl mu/A212A) contains all signal-processing functions and supports all operating modes, including test modes and selection of either 1200 bit/s QPSK or 300 bit/s FSK operation. The modem offers such features as a coherent digital receiver, call-progress toner monit... View full abstract»

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  • A CMOS facsimile video signal processor

    Publication Year: 1985, Page(s):1179 - 1184
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (791 KB)

    A CMOS image scanning signal processor which can be used for CCITT Group-4 facsimile has been developed. To obtain high-speed processing (5 MHz) and high-precision shading distortion correction (up to 70%), hybrid architecture of digital and analog techniques and parameter setting by software are combined. Image sensor and printer interfaces and a digital processor which can do linear zooming and ... View full abstract»

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  • A monolithic signal processor for a neurophysiological telemetry system

    Publication Year: 1985, Page(s):1185 - 1193
    Cited by:  Papers (21)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1301 KB)

    A micropower signal-processor IC is the key component of an implantable telemetry system for neurophysiology. The bipolar/JFET/I/SUP 2/L chip uses digital and low-noise analog circuitry to amplify, filter, and multiplex eight channels of neutral, electrogram, and temperature data from unanesthetized and freely moving animals. Fully integrated continuous-time bandpass amplifiers incorporate a frequ... View full abstract»

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  • A 1.2 GHz frequency synthesizer using a custom-design divide-by-20/21/22/23/24 GaAs circuit

    Publication Year: 1985, Page(s):1194 - 1199
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1133 KB)

    The authors describe the circuit design and the process utilized to fabricate a 1.2 GHz 380-mW divide-by-20/21/22/23/24 GaAs circuit aimed at frequency synthesizer applications. The circuit consists of a 5/6 prescaler, a divide-by-4 circuit, and a four-channel multiplexer. The circuit has been implemented with BFL gates fabricated with 0.7-/spl mu/m planar self-aligned normally-on MESFETs. Further... View full abstract»

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  • A high-performance CMOS power amplifier

    Publication Year: 1985, Page(s):1200 - 1205
    Cited by:  Papers (39)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    A high-performance CMOS power amplifier consisting of a new input stager especially suited to power amplifier applications and a variation on a class AB output stage is presented. The amplifier has been fabricated using a conventional silicon gate p-well process. The configuration results in several performance improvements over previously reported high-output current amplifiers without requiring ... View full abstract»

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  • The synchronous oscillator: a synchronization and tracking network

    Publication Year: 1985, Page(s):1214 - 1226
    Cited by:  Papers (43)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2414 KB)

    The synchronous oscillator (SO) is a free-running oscillator which oscillates at its natural frequency in the absence of an externally applied signal. In the presence of a signal, the oscillator synchronizes with and tracks the input waveform with an acquisition time inversely proportional to the tracking bandwidth. The SO possesses a constant output signal amplitude in the tracking region and an ... View full abstract»

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  • An analytical treatment of the performance of submicrometer FET logic

    Publication Year: 1985, Page(s):1242 - 1251
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (939 KB)

    A self-consistent periodic approach is presented for analyzing the waveforms and for obtaining an analytical expression for the propagation delay of a submicrometer expression for the propagation delay of a submicrometer FET ring oscillator. Rather than using a step input to the inverter to estimate the propagation delay, which greatly overestimates the propagation delay, or an arbitrary ramp inpu... View full abstract»

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  • A novel precision MOS synchronous delay line

    Publication Year: 1985, Page(s):1265 - 1271
    Cited by:  Papers (18)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (781 KB)

    Unlike common delay lines, which are implemented in hybrid technologies, the SDL is implemented in MOS. Thus the SDL obviates the need in certain applications for separate delay-line components, since it can be integrated directly into LSI or VLSI components implemented in common MOS technologies. The SDL was implemented for the first time in a commercial DRAM controller, in which it provided prec... View full abstract»

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  • A 4-Kbit associative memory LSI

    Publication Year: 1985, Page(s):1277 - 1282
    Cited by:  Papers (38)  |  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB)

    A 4-Kb (128 words/spl times/32 bits) CMOS associative-memory large-scale integration (LSI) is described. This LSI has all the functions necessary to achieve a self-operative high-speed data search system. Garbage data collection capabilities have been built into the chip in order to develop self-operative systems. The chip's paralleled and pipelined multiple-response resolver makes high-speed, hig... View full abstract»

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  • A V/SUB be/(T) model with application to bandgap reference design

    Publication Year: 1985, Page(s):1283 - 1285
    Cited by:  Papers (16)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    The authors discuss a new model for the V/SUB be/(T) characteristics of a bipolar transistor. A curvature-compensated bandgap voltage reference scheme based on this model is described. A CMOS circuit configuration to implement the compensation scheme is proposed. It may be suitable for such uses as high-resolution monolithic data acquisition. View full abstract»

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  • Patent abstracts (December 1985)

    Publication Year: 1985, Page(s):1286 - 1292
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  • [Back inside cover - December 1985]

    Publication Year: 1985, Page(s): b1
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  • Laser cutting of aluminium stripes for debugging integrated circuits

    Publication Year: 1985, Page(s):1259 - 1264
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1256 KB)

    The laser cutting of aluminium stripes on a semiconductor integrated circuit chip is investigated using a nitrogen-laser-pumped dye laser with a 12-ns pulse duration of 0.51-μm wavelength. Stripe cutting, without damaging the underlayers, is performed using an aperture projection method in which laser power density is uniformly distributed and edge resolution is sharp. The effects of stripe and... View full abstract»

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  • Numerical simulation of resistive interconnects for integrated circuits

    Publication Year: 1985, Page(s):1252 - 1258
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    When interconnects for integrated circuits have been modeled, it has been normal to consider them only as straight tracks. In any practical circuit this is not the case and a more rigorous analysis is performed by the authors. The effects of corners and T-junctions are analyzed using finite elements and some models are presented which can be used by circuit designers to simulate circuit performanc... View full abstract»

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  • Measurement and modeling of charge feedthrough in n-channel MOS analog switches

    Publication Year: 1985, Page(s):1206 - 1213
    Cited by:  Papers (36)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    Charge feedthrough in analog MOS switches has been measured. The dependence of the feedthrough voltage on the input and tub voltages, device dimensions, and load capacitances was characterized. Most importantly, it was observed that the feedthrough voltage decreases linearly with the input voltage. The significance of this observation when considering harmonic distortion in sample-and-hold circuit... View full abstract»

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  • Low-voltage operational amplifier with rail-to-rail input and output ranges

    Publication Year: 1985, Page(s):1144 - 1150
    Cited by:  Papers (129)  |  Patents (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    An operational amplifier is described which can perform precision signal operations in nearly the full supply voltage range, event when this range is as low as 1.5 V totally. The untrimmed input offset voltage is typically 0.3 mV in an input common-mode (CM) voltage range which extends beyond both supply voltages for about 200 mV. The output voltage can reach each supply rail within 150 mV. A nest... View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief

Jan Craninckx 
Imec
Kapeldreef 75
B-3001 Leuven, Belgium 
jssc.craninckx@gmail.com