Scheduled System Maintenance
On Saturday, December 10, single article sales and account management will be unavailable from 5:00 AM-7:30 PM ET.
We apologize for the inconvenience.
By Topic

IEE Proceedings - Computers and Digital Techniques

Issue 5 • Sep 1996

Filter Results

Displaying Results 1 - 14 of 14
  • Functionally asynchronous array processor for morphological filtering of greyscale images

    Publication Year: 1996, Page(s):273 - 281
    Cited by:  Papers (3)  |  Patents (9)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1268 KB)

    The design of a fine-grain asynchronous VLSI array processor is presented. It demonstrates how asynchronism can be exploited both at functional and architectural levels. A joint algorithm-architecture study that has resulted in the design of a 16×16 processor array is described, and the design flow used to implement both data-paths and control parts is presented. This is based on a standard ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Superscalar instruction issue in an asynchronous microprocessor

    Publication Year: 1996, Page(s):266 - 272
    Cited by:  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (652 KB)

    The implementation of the instruction issuer for a superscalar asynchronous microprocessor (SCALP) is described as a case study in asynchronous design. The issuer accepts five instructions at a time from the memory interface and issues them out of order to five parallel functional units. SCALP's architecture is designed to reduce the complexity of the instruction issuer by removing the need to det... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and implementation of a GaAs systolic floating-point processing element

    Publication Year: 1996, Page(s):325 - 330
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (628 KB)

    The design and layout of a prototype single precision systolic floating-point processing element (PE) is described. It is intended for use in a class of systolic array processors which perform matrix computations. Each PE is constructed from a digit-serial systolic ring of four programmable cells and performs floating-point multiplication and accumulation. A single PE has been fabricated in a 0.8 ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Asynchronous implementation of the SCPP-A counterflow pipeline processor

    Publication Year: 1996, Page(s):287 - 294
    Cited by:  Papers (3)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (748 KB)

    The SCPP-A design problem posed by C.E. Molnar and H. Schols describes an abstraction of the Sproull counterflow pipeline processor which mainly concentrates on pipeline control. Although this problem can be specified concisely, it raises design issues that are intrinsically difficult to deal with. An asynchronous implementation of SCPP-A is presented, where the speed of the resulting circuitry is... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Delayed precise invalidation-a software cache coherence scheme

    Publication Year: 1996, Page(s):337 - 344
    Cited by:  Patents (14)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (824 KB)

    Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence scheme named `delayed precise invalidation' (DPI). DPI is based on compiler-time markings of references and a hardware local invalidation of state data in parallel and selectively. With a small amount of additional hardware ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rotary pipeline processors

    Publication Year: 1996, Page(s):259 - 265
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1008 KB)

    The rotary pipeline processor is a new architecture for superscalar computing. It is based on a simple and regular pipeline structure which can support several ALUs for efficient dispatching of multiple instructions. Values flow around a rotary pipeline, constrained by local data dependencies. During normal operation the control circuits are not on the critical path and performance is only limited... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Functional testing of pipelined processors

    Publication Year: 1996, Page(s):318 - 324
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (596 KB)

    A new method to generate tests for pipelined microprocessors is presented. It concentrates on testing the interlock mechanisms of the instruction pipeline. A new instruction execution model is introduced. A procedure that minimally generates tests to detect any pipeline dependency violations is developed. This procedure is intended to augment current test approaches. A derivation of the test seque... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Asynchronous FPGA architectures

    Publication Year: 1996, Page(s):282 - 286
    Cited by:  Papers (28)  |  Patents (22)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (524 KB)

    Field programmable gate arrays (FPGAs) are of increasing importance as processor support devices, and as computational devices in their only right. Current synchronous FPGA architectures create problems for the implementation of asynchronous circuits, due to their creation of hazards, reordering of signals and lack of arbitration. The paper examines how the first generation of asynchronous FPGA ar... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Estimating power consumption of CMOS circuits modelled as symbolic neural networks

    Publication Year: 1996, Page(s):331 - 336
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (632 KB)

    The authors propose a new approach to the problem of estimating the average power consumption of a CMOS combinational circuit which is based on neural models. Given the gate level description of a circuit, they build the corresponding Hopfield neural network, store it, calculate the energy dissipated by the network and, finally, derive the power dissipated by the original circuit. All the operatio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Verification of speed-independent data-path circuits

    Publication Year: 1996, Page(s):295 - 300
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (624 KB)

    The paper demonstrates that verification techniques developed for relatively large, synchronous circuits can be applied to speed-independent, self-timed circuits. Local formulas are introduced which provide a natural way to specify the input/output behaviour of data-path circuits. The validity of a local formula is independent of the order in which the operations occur in a speed-independent circu... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testable on-the-fly carry-save multiplier by alternating input data

    Publication Year: 1996, Page(s):345 - 348
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (372 KB)

    Montuschi and Ciminiera (1993) presented a carry-save multiplier without final addition. By utilising the don't-care minterms in the original on-the-fly conversion logic and by modifying the summand circuits, the proposed carry-save multiplier can become a concurrent error detection (CED) scheme using a time redundancy technique, called the `alternating logic' (AL) approach, under the cell fault m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architectural considerations for a self-timed decoupled processor

    Publication Year: 1996, Page(s):251 - 258
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (652 KB)

    Self-timed processor designs offer several advantages over traditional synchronous designs. Further, when an asynchronous philosophy is incorporated at every stage of the design, the microarchitecture is more closely linked to the basic structures of the self-timed circuits themselves, and the resulting processor is quite simple and elegant. The Fred architecture presented here is an example of su... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a low-latency asynchronous adder using speculative completion

    Publication Year: 1996, Page(s):301 - 307
    Cited by:  Papers (35)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (748 KB)

    A new general method for designing asynchronous datapath components, called speculative completion, is introduced. The method has many of the advantages of a bundled data approach, such as the use of single-rail synchronous datapaths, but it also allows early completion. As a case study, the method is applied to the high-performance parallel BLC adder design of Brent and Kung (1982). Through caref... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic scheduling in RISC architectures

    Publication Year: 1996, Page(s):309 - 317
    Cited by:  Papers (7)  |  Patents (29)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1028 KB)

    Multithreaded processors support a number of execution contexts, and switch contexts rapidly in order to tolerate highly latent events such as external memory references. Existing multithreaded architectures are implicitly based on the assumption that latency tolerance requires massive parallelism, which must be found from diverse contexts. The authors have carried out a quantitative analysis of t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.