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IEE Proceedings - Computers and Digital Techniques

Issue 6 • Nov 1995

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Displaying Results 1 - 9 of 9
  • Spatial bounding of complex CSG objects

    Publication Year: 1995, Page(s):431 - 439
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1400 KB)

    Several computer graphics algorithms (such as ray-tracing) heavily relate their performances to the efficiency of the tests of intersection between the rays of a light source and the objects of a synthetic scene. Some solid modelling and robotics algorithms need also to test quickly the possible interferences of the different parts of a system such as the arms of different robots. To speed-up the ... View full abstract»

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  • Concurrent error detection in array multipliers by BIDO

    Publication Year: 1995, Page(s):425 - 430
    Cited by:  Papers (9)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (468 KB)

    Array multipliers consist of full adders (FAs). When the sums and carrys are propagated down through the array, each row of FAs is used only once. Most FAs are doing no useful work at any given time. The authors design a concurrent error-detectable array multiplier using bidirectional operation (BIDO). The BIDO implementation employs the inherent idle FAs in an array multiplier to perform the repe... View full abstract»

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  • Novel design of arithmetic coding for data compression

    Publication Year: 1995, Page(s):419 - 424
    Cited by:  Papers (13)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (488 KB)

    The paper presents a novel software and hardware design of a universal arithmetic coding algorithm where 256 ASCII codes of different symbols, as a specific example, are included in the alphabet. Essentially, the two coding equations are modified by specifying the code values as the lower end-point value of the coding range and the width of this range. Therefore the procedures of sending output co... View full abstract»

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  • Design and hardware architectures for dynamic Huffman coding

    Publication Year: 1995, Page(s):411 - 418
    Cited by:  Papers (9)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (772 KB)

    To date, dynamic Huffman coding has not been available for high-speed applications because the tree updating spends a lot of time by current adaptive Huffman coding hardware. The authors present concurrent techniques and the parallel hardware architectures for dynamic Huffman encoding and decoding. For step reduction, they employ the concurrent algorithm for encoding as well as proposing the frequ... View full abstract»

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  • Anatomy of a simulation backplane

    Publication Year: 1995, Page(s):377 - 385
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (888 KB)

    The paper describes how mixed signal simulation has been performed using a simulation backplane. This work is based on the draft standard for a simulation backplane, published by the CAD framework initiative. The simulation backplane allows two or more circuit, logic or behavioural simulators to be coupled. A circuit is partitioned between the simulators, and changes in analogue and digital signal... View full abstract»

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  • Deadlock-free wormhole routing algorithms for star graph topology

    Publication Year: 1995, Page(s):395 - 400
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (588 KB)

    For constructing massively parallel multicomputers with over 5000 processing nodes, the star graph topology is known to be better than the hypercube in terms of the average routing distance, the number of links per node, and the fault diameter. The authors present two deadlock-free algorithms for routing in star graph, assuming the wormhole routing model. Both the algorithms use the concept of vir... View full abstract»

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  • Effects of technology mapping on fault-detection coverage in reprogrammable FPGAs

    Publication Year: 1995, Page(s):407 - 410
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (324 KB)

    Although field-programmable gate arrays (FPGAs) are tested by their manufacturers prior to shipment, they are still susceptible to failures in the field. In this paper test vectors generated for the emulated (i.e. mission) circuit are fault-simulated on two different models: the original view of the circuit, and the design as it is mapped to the FPGA's logic cells. Faults in the cells and in the p... View full abstract»

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  • Adaptive wormhole routing in tori with faults

    Publication Year: 1995, Page(s):386 - 394
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (964 KB)

    The authors present a method to enhance wormhole routing algorithms for deadlock-free fault-tolerant routing in tori. They consider arbitrarily-located faulty blocks and assume only local knowledge of faults. Messages are routed via shortest paths when there are no faults, and this constraint is only slightly relaxed to facilitate routing in the presence of faults. The key concept used is that, fo... View full abstract»

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  • Technique to minimise area overhead for delay-driven clustering

    Publication Year: 1995, Page(s):401 - 406
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (592 KB)

    The paper presents heuristics to the area overhead for delay-driven clustering of combinational circuits under I/O and area constraints. The authors start with a clustering which aims at minimal path delay. They then propose several set covering heuristics to minimise the number of clusters while satisfying the constraints and preserving the timing. Moreover, they propose a hierarchical clustering... View full abstract»

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