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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 4 • Dec. 1995

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Displaying Results 1 - 4 of 4
  • Placement and routing tools for the Triptych FPGA

    Publication Year: 1995, Page(s):473 - 482
    Cited by:  Papers (72)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1349 KB)

    Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques ... View full abstract»

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  • Performance evaluation for application-specific architectures

    Publication Year: 1995, Page(s):483 - 490
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    Performance evaluation is critical for the minimization of design cost. It consists of two parts: modeling the underlying hardware engine and evaluating the performance of the application code for the model developed in the first part. In this paper, we propose a new parameterized model for application-specific architectures and present a retargetable scheduler for performance evaluation. The mode... View full abstract»

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  • The Triptych FPGA architecture

    Publication Year: 1995, Page(s):491 - 501
    Cited by:  Papers (22)  |  Patents (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1222 KB)

    Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance. This is done by allowing a per-mapping tradeoff between logic and routing ... View full abstract»

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  • A new architecture for the automatic design of custom digital neural network

    Publication Year: 1995, Page(s):502 - 506
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    This brief presents a novel high-performance architecture for implementation of custom digital feed forward neural networks, without on-line learning capabilities. The proposed methodology covers the entire design flow of a neural application, by addressing the internal neuron's structure, the system level organization of the processing elements, the mapping of the abstract neural topology (obtain... View full abstract»

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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu