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FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on

10-13 April 1994

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  • Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • Emulation of the Sparcle microprocessor with the MIT Virtual Wires emulation system

    Publication Year: 1994, Page(s):14 - 22
    Cited by:  Papers (10)  |  Patents (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Describes a complete FPGA-based emulation software system using Virtual Wires technology and present the results of emulating an 18K-gate ASIC implementation of a modified Sparc microprocessor. Virtual Wires overcomes the pin-count limitation that formerly restricted the efficiency of FPGA-based logic emulators. The MIT Virtual Wires softwire compiler accepts a netlist description of the system to... View full abstract»

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  • Pin assignment for multi-FPGA systems

    Publication Year: 1994, Page(s):11 - 13
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    There is currently great interest in using systems of FPGAs for logic emulators, custom computing devices, and software accelerators. An important step in making these technologies more generally useful is to develop completely automatic mapping tools from high-level specifications to FPGA programming files. We examine one step in this automatic mapping process, the selection of FPGA pins to use f... View full abstract»

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  • A field programmable multi-chip module (FPMCM)

    Publication Year: 1994, Page(s):1 - 10
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB)

    Multi-chip module (MCM) packaging can reduce the cost and increase the utility of field programmable systems. We are currently developing a first generation field programmable multi-chip module (FPMCM) as a test vehicle for a particular MCM technology. We present the advantages of MCM for field programmable systems and develop analytical models for estimating the capacity of FPMCM architectures ba... View full abstract»

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  • Behavioral synthesis for FPGA-based computing

    Publication Year: 1994, Page(s):125 - 132
    Cited by:  Papers (9)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    We describe how a behavioral synthesis system can be used to create designs for FPGA-based computing systems directly from a specification of the desired algorithm. This higher level of specification reduces design times and design errors. Our target hardware is called the Rasa Board and is composed of three Xilinx FPGAs interconnected with Aptix Field Programmable Interconnect Chips. We address t... View full abstract»

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  • From high level programming model to FPGA machines

    Publication Year: 1994, Page(s):119 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    This paper presents an approach for deriving a FPGA machine from a high level parallel programming model. The model is based on the chemical reaction metaphor : the data structure is a multiset and the computation can be seen as a succession of chemical reactions consuming and producing new elements according to specific rules. Von Newman architecture are not suited to this programming style; we s... View full abstract»

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  • Virtual hardware for graphics applications using FPGAs

    Publication Year: 1994, Page(s):49 - 58
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    The suitability of FPGA devices for implementing graphics algorithms is analysed by a series of experiments. The performance of simple and complicated graphics algorithms on two kinds of FPGAs are compared with the performance of existing custom graphics chips and against general-purpose processors with specialised instruction sets. Various architectures for incorporating FPGA-based systems into g... View full abstract»

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  • A reconfigurable compute engine for real-time vision automata prototyping

    Publication Year: 1994, Page(s):91 - 100
    Cited by:  Papers (12)  |  Patents (78)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    Describes a reconfigurable computer engine called the Data-Flow Functional Computer (DFFC), which is dedicated to rapid prototyping of real-time vision automata. The computer consists of a regular 3D array of very coarse grain application-specific FPGAs, called the `field-programmable operator array' (FPOA). Each FPOA includes two configurable data paths and ten input/output ports. Specific develo... View full abstract»

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  • A case study on hardware/software partitioning

    Publication Year: 1994, Page(s):111 - 118
    Cited by:  Papers (8)  |  Patents (74)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user p... View full abstract»

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  • Field programmable gate array based reconfigurable preprocessor

    Publication Year: 1994, Page(s):40 - 48
    Cited by:  Papers (16)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Custom hardware implementations of preprocessors are seldom reusable, flexible enough to allow algorithm exploration or quickly realized. The Configurable Hardware Algorithm Mappable Preprocessor (CHAMP) technology is a solution to these problems. Recent developments in FPGA hardware and software have made a reconfigurable preprocessor with custom hardware performance but generic hardware flexibil... View full abstract»

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  • Finding lines and building pyramids with SPLASH 2

    Publication Year: 1994, Page(s):155 - 163
    Cited by:  Papers (25)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    This paper describes the design and implementation of two image-processing algorithms using the SPLASH 2 custom computing platform. SPLASH 2 is a reconfigurable system that can be tailored to perform a wide variety of tasks. The particular tasks discussed here are the Hough transform. A well-known technique for detecting lines in an image, and pyramid generation. The process of transforming a sing... View full abstract»

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  • Density enhancement of a neural network using FPGAs and run-time reconfiguration

    Publication Year: 1994, Page(s):180 - 188
    Cited by:  Papers (32)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    Run-time reconfiguration is a way of more fully exploiting the flexbility of reconfigurable FPGAs. The run-time reconfiguration artificial neural network (RRANN) uses ran-time reconfiguration to increase the hardware density of FPGAs. The RRANN architecture also allows large amounts of parallelism to be used and is very scalable. RRANN divides the back-propagation algorithm into three sequential e... View full abstract»

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  • Hardware-software codesign of multidimensional programs

    Publication Year: 1994, Page(s):82 - 90
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    Presents a method for parametrised partitioning of multidimensional programs for acceleration using a hardware coprocessor. The method involves a divide-and-conquer structure, with the “divide” and “merge” phases carried out by a general-purpose processor, while the “conquer” phase is handled by application-specific hardware. The partitioning strategy has been c... View full abstract»

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  • DPGA-coupled microprocessors: commodity ICs for the early 21st Century

    Publication Year: 1994, Page(s):31 - 39
    Cited by:  Papers (64)  |  Patents (66)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    During the past decade, the microprocessor has become a key commodity component for building all kinds of computational systems. During this time frame, large reconfigurable logic arrays have exploited the same advances in IC fabrication technology to emerge as viable system building blocks. Looking at both the technology prospects and application requirements, there is compelling evidence that mi... View full abstract»

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  • Compiling to the gate level for a reconfigurable co-processor

    Publication Year: 1994, Page(s):147 - 154
    Cited by:  Papers (9)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    This paper describes a programmable coprocessor. A C-compiler has been written which compiles C code to the gate level relieving the programmer of the onerous task of programming the coprocessor. As not all of the code in most C programs will fit into the coprocessors FPGA, programs are first compiled using a standard C compiler. These programs are then profiled to determine which parts of the cod... View full abstract»

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  • An FPGA-based custom coprocessor for automatic image segmentation applications

    Publication Year: 1994, Page(s):172 - 179
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    We describe a customized computing platform we are developing to accelerate a computer vision application. An FPGA-based coprocessor solution is derived which accelerates most of the compute-intensive calculations of a template deforming image segmentation algorithm. Design issues are identified and performance results reported. The results are parameterized so that alternative solutions can be ev... View full abstract»

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  • Global control synthesis for an MIMD/FPGA machine

    Publication Year: 1994, Page(s):72 - 81
    Cited by:  Papers (8)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Embedding a FPGA circular array into MIMD architectures allows one to synthesize fine-grain circuits for global computation support. These circuits operate concurrently with the distributed applications. They provide specific speed-up or additional services, such as communication protocols or global controllers. This article describes an architectural model for such controllers with practical exam... View full abstract»

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  • The Nano Processor: a low resource reconfigurable processor

    Publication Year: 1994, Page(s):23 - 30
    Cited by:  Papers (23)  |  Patents (91)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    Reconfigurable logic systems approach the performance of application-specific integrated circuits (ASICs) while retaining much of the generality of conventional computing systems through reconfiguration. Unfortunately, the development of these systems, unlike conventional software systems, is hardware-intensive, requiring significant hardware development time. One way to introduce a more flexible ... View full abstract»

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  • PAM programming environments: practice and experience

    Publication Year: 1994, Page(s):133 - 138
    Cited by:  Papers (19)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Digital Equipment's Paris Research Laboratory started to investigate the use of FPGA-based reconfigurable hardware accelerators in 1988. We call them PAMs for Programmable Active Memories. Over the past six years, we have designed and implemented four generations of PAM hardware and four generations of PAM programming environments. Several dozen people, ranging from inexperienced students to senio... View full abstract»

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  • An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

    Publication Year: 1994, Page(s):101 - 110
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    PRISM, a computer architecture consisting of a general-purpose core processor and a reconfigurable FPGA platform, was designed to bridge the gap between general-purpose and specialized computers. The proof-of-concept system, PRISM-I suffers from several limitations, principal among them being: single bus-cycle restriction on the evaluation time of the function synthesized on an FPGA, inability to ... View full abstract»

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  • Comparing the performance of FPGA-based custom computers with general-purpose computers for DSP applications

    Publication Year: 1994, Page(s):164 - 171
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    When FPGA logic circuits are incorporated within a stored-program computer, the result is a machine where the programmer can design both the software and the hardware that will execute that software. This paper first describes some of the more important custom computers, and their potential weakness as DSP implementation platforms. It then describes a new custom computing architecture which is spe... View full abstract»

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  • FPGA-based stochastic neural networks-implementation

    Publication Year: 1994, Page(s):189 - 198
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    Reconfigurable field-programmable gate arrays (FPGAs) provide an effective programmable resource for implementing hardware-based artificial neural networks (ANNs). They are low cost, readily available and reconfigurable-all important advantages for ANN applications. However, FPGAs lack the circuit density necessary to implement large parallel ANNs with many thousands of synapses. This paper presen... View full abstract»

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  • A reconfigurable Monte-Carlo clustering processor (MCCP)

    Publication Year: 1994, Page(s):59 - 65
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    A generic Monte Carlo problem architecture, implemented earlier in a dedicated FPGA computer (Monaghan, O'Brien and Noakes, 1991; Monaghan, 1993; Monaghan and Cowen, 1993), is extended to incorporate a wider range of more complex Monte Carlo and percolation problems. The new algorithms, which are implemented in the same computer architecture, execute an order of magnitude faster than on comparable... View full abstract»

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  • CAFCA (Compact Accelerator For Cellular Automata): the metamorphosable machine

    Publication Year: 1994, Page(s):66 - 71
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    Partial differential equations have conventionally formed a basis for mathematical models of continuous systems. Cellular automata provide an alternative approach. The large scope of applications of cellular automata (in biology, physics, operational research, sociology, computer science and so on) will surely increase the need of such a tool. The basic constitutive cells are discrete and ideally ... View full abstract»

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  • A reconfigurable data-driven ALU for Xputers

    Publication Year: 1994, Page(s):139 - 146
    Cited by:  Papers (6)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    A reconfigurable data-driven datapath architecture for ALUs is presented which may be used for custom computing machines (CCMs), Xputers (a class of CCMs) and other adaptable computer systems as well as for rapid prototyping of high speed datapaths. Fine grained parallelism is achieved by using simple reconfigurable processing elements which are called datapath units (DPUs). The word-oriented data... View full abstract»

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