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Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era

27-28 April 2000

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  • Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era

    Publication Year: 2000
    Request permission for commercial reuse | PDF file iconPDF (371 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 2000, Page(s): 161
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    Freely Available from IEEE
  • Validation of complex designs through hardware prototyping

    Publication Year: 2000, Page(s):149 - 154
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    Functional validation of complex designs by means of hardware prototyping (emulation) is a major tool used by industry to improve the validation quality at the different chip design program phases. However, fitting a design into emulation is not a simple task. Lots of elements collide in orthogonal domains, while trying to get emulation going. This paper goes through selected topics in ramping up ... View full abstract»

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  • RT-level interconnect optimization in DSM regime

    Publication Year: 2000, Page(s):143 - 148
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    We propose global-net clustering based RT-level datapath design methodology. Static timing analysis identifies critical nets and critical primary input/output paths. Net clustering (based shared macro-cells and criticality) yields clusters wherein each cluster has strongly interdependent nets. Clusters and nets within every cluster are prioritized based on number of critical nets, number of nets, ... View full abstract»

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  • Alternative architectures for video signal processing

    Publication Year: 2000, Page(s):5 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    This paper looks at trends in architectures for video processing. As levels of integration has increased, video architectures have moved from dedicated to programmable. Programmable architectures continue to evolve as we move into the systems-on-silicon era. The promise of integrated memory systems is a particularly appealing prospect for improved video processing architectures View full abstract»

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  • An algorithmic approach to building datapath multipliers using (3,2) counters

    Publication Year: 2000, Page(s):135 - 139
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    Traditionally multipliers have been laid out manually, using simple delay models for the counters. However, at deep submicron feature sizes, these delay models do not accurately model the resulting delays. Therefore, an algorithmic approach to the design of the multiplier is required. This paper presents an algorithm that connects the counters of the multiplier, under the constraint of a limited n... View full abstract»

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  • Mead-Conway VLSI design approach and system design challenges ahead

    Publication Year: 2000
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (24 KB)

    What should the students of today be learning and doing to prepare them for system design 10 years from now? What will be the biggest challenges facing them at that time? Then too, where are the biggest opportunities for research impact right now? To help us think about such questions, we'll look back 25 years and reflect on some lessons from the early VLSI adventures of the late 70's. We'll see h... View full abstract»

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  • A system-level approach to power/performance optimization in wearable computers

    Publication Year: 2000, Page(s):15 - 20
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1236 KB)

    The paper describes a system-level design approach to the power and performance of Carnegie Mellon's wearable computers dedicated to speech processing-the Speech Translator Smart Modules. While processor speed and type affect power consumption and performance, memory size and type of secondary storage have a significant influence as well. A system-level approach to power/performance optimization i... View full abstract»

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  • Reconfigurable low energy multiplier for multimedia system design

    Publication Year: 2000, Page(s):129 - 134
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multiplier a... View full abstract»

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  • Architectural adaptation in AMRM machines

    Publication Year: 2000, Page(s):75 - 79
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    Application adaptive architectures use architectural mechanisms and policies to achieve system level performance goals. The AMRM project at UC Irvine focuses on adaptation of the memory hierarchy and its role in latency and bandwidth management. This paper describes the architectural principles and first implementation of the AMRM machine proof-of-concept prototype View full abstract»

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  • Improved synchronization methodologies for high performance digital systems

    Publication Year: 2000, Page(s):61 - 66
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    Traditional synchronization methodologies have largely concentrated on the use of a global clock signal to maximize the functional integration possible on the chip. Unfortunately, distribution of a low skew clock signal over the entire die at current clock rates is becoming increasingly difficult. By using a combination of architectural design and delay insensitive data encoding, it is possible to... View full abstract»

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  • Dynamic voltage scaling techniques for distributed microsensor networks

    Publication Year: 2000, Page(s):43 - 46
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB)

    Distributed microsensor networks promise a versatile and robust platform for remote environment monitoring. Crucial to long system lifetimes for these microsensors are algorithms and protocols that provide the option of trading quality for energy savings. Dynamic voltage scaling on the sensor node's processor enables energy savings from these scalable algorithms. We demonstrate dynamic voltage sca... View full abstract»

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  • Fine-grain pipelined asynchronous adders for high-speed DSP applications

    Publication Year: 2000, Page(s):111 - 118
    Cited by:  Papers (30)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    A new asynchronous pipeline scheme (called LPw), and two new pipelined asynchronous adder implementations, are introduced for high-throughput applications such as DSPs for multimedia processing. The pipeline scheme is targeted to dynamic datapaths. A novelty of the approach is that it uses decoupled control for pull-up and pull-down stacks. The adders are pipelined at the gate-level and... View full abstract»

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  • On-line error detection in multiplexor based FPGAs

    Publication Year: 2000, Page(s):155 - 159
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (28 KB)

    In this paper we introduce a new method for incorporating on-line error detection capabilities in multiplexor based FPGAs. The advantages, with respect to traditional off-line testing are that there is no need to determine test vectors and no need for storage of the test vectors and correct output responses. We have shown that all single faults in the circuit are detectable using our method. Furth... View full abstract»

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  • PicoRadio: Ad-hoc wireless networking of ubiquitous low-energy sensor/monitor nodes

    Publication Year: 2000, Page(s):9 - 12
    Cited by:  Papers (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    One of the most compelling challenges of the next decade is the solution of the “last meter” problem, which extends the network into the end-user data-collection and monitoring devices. This paper discusses the challenges and opportunities of a “PicoRadio Network” that supports the assembly of an an-hoc wireless network of meso-scale, low-cost and low-energy sensor and moni... View full abstract»

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  • A low-latency FIFO for mixed-clock systems

    Publication Year: 2000, Page(s):119 - 126
    Cited by:  Papers (42)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    This paper presents a low-latency FIFO design that interfaces subsystems on a chip working at different speeds. First, a single-clock domain design is introduced, which is then used as a basis for a mixed-clock version. Finally, the design is adapted to work between subsystems with very long interconnection delays. The designs can be made arbitrarily robust with regard to metastability and clock f... View full abstract»

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  • Emerging trends in VLSI test and diagnosis

    Publication Year: 2000, Page(s):21 - 27
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    As the move to very deep submicron VLSI devices pushes the threshold of semiconductor technology, conventional test and diagnosis methods become inadequate and costly. The new level of complexity driven by core-based system-chips demands that designers alter the way they approach chip development in order to keep up with diminishing time-to-market requirements and stay within budgets. Embedded tes... View full abstract»

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  • An empirical and analytical comparison of delay elements and a new delay element design

    Publication Year: 2000, Page(s):81 - 86
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    This paper comprehensively reviews five different delay element architectures for use in CMOS VLSI design. The first four delay elements that we analyze are already in general use; they are the transmission gate, cascaded inverters, thyristor, and voltage-controlled delay element. The fifth delay element, a transmission gate with Schmitt trigger, is a new architecture that we are proposing in this... View full abstract»

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  • Low power VLSI architecture for 2D-mesh video object motion tracking

    Publication Year: 2000, Page(s):67 - 72
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    This paper presents a low power VLSI architecture for video object motion tracking. Power has been reduced at both algorithmic and arithmetic levels. The video object is modeled as a 2D hierarchical structured mesh, where the deformation of the mesh represents the dynamics of the object across the video sequence. The algorithm benefits from the small number of bits that describe the mesh topology.... View full abstract»

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  • Reducing the power consumption in FPGAs with keeping a high performance level

    Publication Year: 2000, Page(s):47 - 52
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    Power consumption is becoming an important constraint in VLSI design because of the increase of wireless and portable battery powered applications. On the other hand, the use of Field Programmable Gate Arrays (FPGAs) has been increasing largely due to the ability to rapidly develop prototypes with reduced development times and costs. A well known technique for low power operation in VLSI using the... View full abstract»

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  • Multilanguage design of a robot arm controller: Case study

    Publication Year: 2000, Page(s):29 - 34
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    This paper discusses a case study, the multilanguage design of a robot arm controller. The system is composed of two parts: the controller and the motors of the robot arm. The design starts with a multilanguage system-level specification. SDL was used for the description of the controller and Matlab was used for the description of the physical behavior of the motors. The multilanguage design flow ... View full abstract»

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  • Specification and validation of information processing systems by process encapsulation and symbolic execution

    Publication Year: 2000, Page(s):89 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    A process notation based on a functional partitioning of a new system is proposed as a high-level codesign model for specification, evaluation, and implementation purposes. A well-defined computational model allows the synchronization and activation of concurrent processes. The design environment includes the refinement steps from scheduling with dynamic processes via simplified scheduling/executi... View full abstract»

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  • Multiple access caches: Energy implications

    Publication Year: 2000, Page(s):53 - 58
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    In this paper, we model and evaluate the energy consumption of three different multiple access cache architectures that target the reduction of access latencies of associative caches. Further, we compare their energy consumption with that of traditional direct-mapped and set-associative caches. Among all the cache architectures, the most recently used cache is found to be most energy-efficient for... View full abstract»

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  • Instruction scheduling based on energy and performance constraints

    Publication Year: 2000, Page(s):37 - 42
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper we present and eva... View full abstract»

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  • Interaction in language based system level design using an advanced compiler generator environment

    Publication Year: 2000, Page(s):97 - 102
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    Computer-aided synthesis of digital circuits from behavioural level specifications offers an effective way to deal with the increasing complexity of digital hardware design. A high-level synthesis tool transforms an abstract algorithmic description into a detailed register transfer level implementation. Even though considerable research has taken place, regarding high-level synthesis, practical im... View full abstract»

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