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Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

20-22 May 1999

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  • Proceedings 1999 29th IEEE International Symposium on Multiple-Valued Logic (Cat. No.99CB36329)

    Publication Year: 1999
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (254 KB)

    Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the ori... View full abstract»

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  • Author index

    Publication Year: 1999, Page(s): 302
    Request permission for commercial reuse | PDF file iconPDF (120 KB)
    Freely Available from IEEE
  • Research on the similarity among precomplete sets preserving m-ary relations in partial k-valued logic

    Publication Year: 1999, Page(s):136 - 139
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (64 KB)

    In multiple-valued logic theories, the characterization of Sheffer functions is an important problem, it includes the decision and construction for Sheffer functions in Pk and Pk*. The solution of these problems depends on the solution of the decision problem for completeness in Pk and Pk*, and reduced to determining the minimal coverings of precomplete ... View full abstract»

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  • The number of cascade functions

    Publication Year: 1999, Page(s):131 - 135
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Cascade function is a Boolean function which can be implemented by a so-called cascade network. An n input cascade network is a circuit built with n-1 two-input-one-output gates (i.e., dyadic operations) such that at least one input of each gate is a network input. By arranging the inputs in a proper order these networks can be presented in a “cascade” shape, which is the origin of the... View full abstract»

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  • Clarifying the axioms of Kleene algebra based on the method of indeterminate coefficients

    Publication Year: 1999, Page(s):125 - 130
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    After introducing the method of indeterminate coefficients, by which we can derive all finite models satisfying a given set of axioms, we derive all models of 8 elements of Kleene algebra by using the method, and find out many examples of a set of independent and complete axioms of Kleene algebra by checking whether each axiom in Kleene algebra is independent from others or not based on the method View full abstract»

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  • Development of quantum functional devices for multiple-valued logic circuits

    Publication Year: 1999, Page(s):2 - 9
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Quantum functional devices exhibiting unique current-voltage characteristics are reported for the application of multiple-valued logic circuits. Multiple negative-differential-resistance (NDR) characteristics in drain current-voltage characteristics are demonstrated by using multiple-junction surface tunnel transistors (MJ-STTs). Some multiple-valued logic gates such as inverter and literal are im... View full abstract»

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  • A super switch algebra for quantum device based systems

    Publication Year: 1999, Page(s):118 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1184 KB)

    In this paper a multiple-valued algebra, super switch algebra, is formalized. The algebra is well suited for the design of quantum device based multiple-valued systems. A minimization algorithm based on this algebra is proposed. This new algebraic algorithm has some advantages over the existing map-based procedure and subfunction-based algorithm. Benchmark functions are minimized and the results a... View full abstract»

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  • Logical model for representing uncertain statuses of multiple-valued logic systems realized by min, max and literals

    Publication Year: 1999, Page(s):110 - 115
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1704 KB)

    This paper discusses a logical model which is suitable for representing uncertain statuses existing in multiple-valued logic systems realized by minimum, maximum and literals. Then, some of the mathematical properties of functions defined by the logical model are presented View full abstract»

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  • Ternary multiplication circuits using 4-input adder cells and carry look-ahead

    Publication Year: 1999, Page(s):174 - 179
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1076 KB)

    We introduce a new implementation of a ternary adder with four inputs and two outputs. This ternary adder reduces the number of digits in a multiplication compared with a binary multiplication. One advantage of the ternary adder is that four instead of three inputs within a binary representation will be summed up. In this paper we will compare the complexity of binary against ternary multipliers. ... View full abstract»

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  • The output permutation for the multiple-valued logic minimization with universal literals

    Publication Year: 1999, Page(s):105 - 109
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (40 KB)

    This paper shows the effectiveness of an output permutation for the implementation of current-mode CMOS circuits. A combination of a simple function and an output permutation can realize a difficult function and cost for the combination will be lower than the cost for a difficult function. The output permutation can be realized by a universal literal and we can calculate the cost. We first examine... View full abstract»

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  • Shared multiple-valued decision diagrams for multiple-output functions

    Publication Year: 1999, Page(s):166 - 172
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    In this paper, we propose a method to represent multiple-output functions using shared multiple-valued decision diagrams (SMDDs). We show an algorithm for pairing the input variables of binary decision diagrams (BDDs). We also present the pair sifting that moves pairs of 4-valued input variables to speed up the normal sifting, and to produce compact SMDDs. The size of the SMDD is the total number ... View full abstract»

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  • On the number of multilinear partitions and the computing capacity of multiple-valued multiple-threshold perceptrons

    Publication Year: 1999, Page(s):208 - 213
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    We introduce the concept of multilinear partition of a point set V⊂Rn and the concept of multilinear separability of a function f:V→K={0, ..., k-1}. Based on well known relationships between linear partitions and minimal pairs, we derive formulae for the number of multilinear partitions of a point set in general position and of the set K2. The (n, k, s)-perceptrons p... View full abstract»

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  • Partial clones and their generating sets

    Publication Year: 1999, Page(s):85 - 90
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    We present some of our recent results on partial clones. Let A be a non singleton finite set. For every maximal clone C on A, we find the maximal partial clone on A that contains C. We also construct families of finitely generated maximal partial clones as well as a family of not finitely generated maximal partial clones on A. Furthermore, we study the pairwise intersections of all maximal partial... View full abstract»

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  • State assignment techniques in multiple-valued logic

    Publication Year: 1999, Page(s):220 - 225
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    Multiple-Valued Logic (MVL) functions are implemented via Boolean multiple-wire arrangements where a careful state assignment methodology is used to ensure efficient implementation regimes. A `power of N' module is proposed for GF (23). The method avoids the need to factorize the polynomial and circuits can be realised using a combination of NOT AND and XOR functions. In addition, a nov... View full abstract»

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  • Multiple-valued minimization to optimize PLAs with output EXOR gates

    Publication Year: 1999, Page(s):99 - 104
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We present techniques to minimize EX-SOPs, which is an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. We conjecture that, when n is sufficien... View full abstract»

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  • Synthesis of multiple-valued decision diagrams using current-mode CMOS circuits

    Publication Year: 1999, Page(s):160 - 165
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    In this paper, an algorithm for generating modular designs of Ordered Multiple Decision Diagrams (OMDDs) for Current-Mode CMOS Logic (CMCL) implementation is introduced. The OMDD structures for a set of twelve benchmark circuits from the LGSynth93 using radices ranging from r=2 to r=10 are generated and compared in terms of size and speed. It is observed that MODDs with radices r∈(2, 4, 8) re... View full abstract»

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  • On axiomatization of conditional entropy of functions between finite sets

    Publication Year: 1999, Page(s):24 - 28
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    In this paper we present a new axiomatization of the notion of entropy of functions between finite sets and we introduce and axiomatize the notion of conditional entropy between functions. The results can be directly applied to logic functions, which can be regarded as functions between finite sets. Our axiomatizations are based on properties of entropy with regard to operations commonly applied t... View full abstract»

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  • Representation theorems and theorem proving in non-classical logics

    Publication Year: 1999, Page(s):242 - 247
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    In this paper we present a method for automated theorem proving in non-classical logics having as algebraic models bounded distributive lattices with certain types of operators. The idea is to use a Priestley-style representation for distributive lattices with operators in order to define a class of Kripke-style models with respect to which the logic is sound and complete. If this class of Kripke-... View full abstract»

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  • Fault characterization and testability considerations in multi-valued logic circuits

    Publication Year: 1999, Page(s):262 - 267
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    With the growing interest and the emergence of various implementations of Multiple-Valued logic (MVL) circuits, testability issues of these circuits are becoming crucial. Fault characterization is an early step in the test generation process. It is aimed at finding fault models that best describe the possible faults expected to occur in a given class of circuits or technology. Layout and device le... View full abstract»

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  • Redundant complex arithmetic and its application to complex multiplier design

    Publication Year: 1999, Page(s):200 - 207
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    This paper presents a class of complex number representations called Redundant Complex Number Systems (RCNSs), which are useful for designing VLSI signal processors with complex arithmetic capability. A redundant complex: number system is defined as an imaginary-radix number system having a redundant integer digit set. This makes possible the construction of high-speed complex arithmetic circuits:... View full abstract»

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  • On some classes of fuzzy information granularity and their representations

    Publication Year: 1999, Page(s):288 - 293
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (76 KB)

    This paper describes some classes of fuzzy information granularity and their representation methods. Fuzzy information granularity introduced by Zadeh is that “granularity relates to clumpiness of structure, while granulation refers to partitioning an object into a collection of granules, with a granule being a clump of objects (points) drawn together by indistinguishability, similarity, pro... View full abstract»

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  • Maximal chains of partial clones containing all idempotent partial functions

    Publication Year: 1999, Page(s):80 - 84
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Let k⩾2 and k be a k-element set. We show that every partial clone containing all idempotent partial functions on k is finitely generated. Moreover we construct maximal chains of length 2k of such partial clones View full abstract»

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  • Structural and behavioral modeling with monadic logics

    Publication Year: 1999, Page(s):142 - 151
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Logic offers the possibility of modeling and reasoning about hardware and software. But which logic? We propose monadic logics of strings and trees as good candidates for many kinds of discrete systems. These logics are natural, decidable, yet substantially more expressive, extensions of Boolean logic. We motivate their applicability through examples View full abstract»

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  • Multivalued binary relations and Post algebras

    Publication Year: 1999, Page(s):10 - 17
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2004 KB)

    This paper deals with a multivalued extension of the concept of a binary relation on a set E. If R is such an r-valued relation on E, far every (x, y)∈E2, there exists exactly one i∈{0, 1, ..., r-1} such that the degree of comparability of (x, y) with respect to R is equal to i. The set of all r-valued relations on E is then equipped with an order relation ⩽ and turns out ... View full abstract»

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  • Down literal circuit with neuron-MOS transistors and its applications

    Publication Year: 1999, Page(s):180 - 185
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    A voltage-mode neuron-MOS(νMOS) down literal circuit which realizes an arbitrary down literal function is proposed. It provides the benefit that the circuit can be easily fabricated by standard CMOS process, instead of the multi-level ion implantation applied in the conventional circuit. It has a variable threshold voltage by way of controlling only two bias voltages. Its noise margin and switc... View full abstract»

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