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2011 Second International Conference on Networking and Computing

Nov. 30 2011-Dec. 2 2011

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  • [Front cover]

    Publication Year: 2011, Page(s): C1
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  • [Title page i]

    Publication Year: 2011, Page(s): i
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  • [Title page iii]

    Publication Year: 2011, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - x
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  • Message from the General Chair

    Publication Year: 2011, Page(s): xi
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  • Message from the Program Committee Chair

    Publication Year: 2011, Page(s): xii
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  • Message from the Steering Chair

    Publication Year: 2011, Page(s): xiii
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  • Organizing Committee

    Publication Year: 2011, Page(s): xiv
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  • Program Committee

    Publication Year: 2011, Page(s):xv - xvii
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  • Workshop Organizers

    Publication Year: 2011, Page(s):xviii - xxi
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  • Reviewers

    Publication Year: 2011, Page(s): xxii
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  • Probabilistic Self-Stabilization and Random Walks

    Publication Year: 2011, Page(s):1 - 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (183 KB) | HTML iconHTML

    A distributed system is said to be probabilistic self-stabilizing, if it eventually converges to legitimate computation with probability 1, starting from any global configuration. Like a self-stabilizing system, a probabilistic self-stabilizing system tolerates any number of transient failures and recovers legitimate computation, but only probabilistically unlike a self-stabilizing system. After i... View full abstract»

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  • Invitation to OpenCL

    Publication Year: 2011, Page(s):8 - 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB) | HTML iconHTML

    The recent advancement in GPU technology has attracted researchers who need intensive computing to the GPU-based computing (GPGPU) field because of its high and inexpensive performance. However, GPGPU programming platforms are traditionally vendor- or hardware-specific, which complicate the access to the computer power of heterogeneous processors from a single host. The recently released OpenCL is... View full abstract»

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  • Virtualized Development and Testing of Embedded Computing Clusters

    Publication Year: 2011, Page(s):17 - 26
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1039 KB) | HTML iconHTML

    Design of customised embedded cluster processing solutions can be difficult for reasons including the large number of unknowns at design time in terms of quantity and type of processors, interconnectivity characteristics and code partitioning, and for reasons relating to inaccessible hardware for software developers. Many of these issues are faced in conventional development projects for generic e... View full abstract»

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  • All about RICC: RIKEN Integrated Cluster of Clusters

    Publication Year: 2011, Page(s):27 - 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1022 KB) | HTML iconHTML

    This is an introduction to RIKEN's supercomputer RICC (RIKEN Integrated Cluster of Clusters), that has been in operation since August 2009. The basic concept of the RICC is "provide high power computational resources for research and development for RIKEN's researchers". Based on this concept, we have been providing for (i) data analysis environment for experimental researchers, (ii) development e... View full abstract»

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  • Self-Stabilizing Small k-Dominating Sets

    Publication Year: 2011, Page(s):30 - 39
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (442 KB) | HTML iconHTML

    A self-stabilizing algorithm, after transient faults hit the system and place it in some arbitrary global state, recovers in finite time without external (e.g., human) intervention. In this paper, we propose a distributed asynchronous silent self-stabilizing algorithm for finding a minimal k-dominating set of at most [n/(k+1)] processes in an arbitrary identified network of size n. We propose a tr... View full abstract»

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  • Fast and Reliable Route Maintenance Protocols for WSN with Crash and Intermittent Failures

    Publication Year: 2011, Page(s):40 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB) | HTML iconHTML

    In this paper, we consider the problem of route maintenance in unstable networks to realize a low latency, highly reliable message delivery in wireless sensor networks (WSNs). In WSNs, each sensor node may suddenly stall due to crash and/or battery drain and the wireless links between adjacent nodes are not reliable enough. Thus, a route maintenance algorithm for WSNs should tolerate both of crash... View full abstract»

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  • Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects

    Publication Year: 2011, Page(s):50 - 57
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    Ethernet has been used for interconnection networks of high-performance computing (HPC) systems that include PC clusters. Although a layer-2 Ethernet topology is limited to a tree structure in order to avoid broadcast storms and deadlocks of frames, various topologies with deadlock-free routing, that include loops, suitable for parallel processing can be used by the application of IEEE 802.1Q VLAN... View full abstract»

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  • Hierarchical Dual-Net: A Flexible Interconnection Network and Its Routing Algorithm

    Publication Year: 2011, Page(s):58 - 67
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    In this paper, we propose a flexible interconnection network, called hierarchical dual-net (HDN), with low node degree and short diameter for constructing a supercomputer of large scale. The HDN is constructed based on a symmetric product graph (base network). A k-level hierarchical dual-net, HDN(B, k, S), contains (2N0)2k/(2×Πi=1... View full abstract»

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  • A GPU Implementation of Computing Euclidean Distance Map with Efficient Memory Access

    Publication Year: 2011, Page(s):68 - 76
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    Recent Graphics Processing Units (GPUs), which have many processing units, can be used for general purpose parallel computation. To utilize the powerful computing ability, GPUs are widely used for general purpose processing. Since GPUs have very high memory bandwidth, the performance of GPUs greatly depends on memory access. The main contribution of this paper is to present a GPU implementation of... View full abstract»

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  • An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles

    Publication Year: 2011, Page(s):77 - 86
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    Field Programmable Gate Arrays (FPGAs) are a dominant implementation medium for digital circuits which are used to embed a circuit designed by users instantly. FPGAs can be used for implementing parallel and hardware algorithms. Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read O... View full abstract»

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  • Automatic Vectorization by Runtime Binary Translation

    Publication Year: 2011, Page(s):87 - 94
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (235 KB) | HTML iconHTML

    Today, most general desktop PCs uses processors that incorporate SIMD (Single Instruction Multiple Data) units. These SIMD units, however, are for the most part underutilized with the exception of a few multimedia applications. As a result, the processing power of modern processors is not fully unleashed. In this research, we propose a system that applies automatic vectorization techniques to bina... View full abstract»

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  • An Implementation of Handshake Join on FPGA

    Publication Year: 2011, Page(s):95 - 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (370 KB) | HTML iconHTML

    This paper shows an implementation of handshake join on field-programmable gate array (FPGA). Handshake join is one of stream join algorithms, proposed by Teubner and Mueller. It can support very high degrees of parallelism and attain unprecedented success in throughput speed in order to achieve efficient support for window-based join in streaming databases. In handshake join, it is necessary to t... View full abstract»

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  • Optimization of Regular Expression Processing Circuits for NIDS on FPGA

    Publication Year: 2011, Page(s):105 - 112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB) | HTML iconHTML

    Recent Network Intrusion Detection System (NIDS) utilizes more and more Regular Expression to describe malicious patterns existing in the content payload of packets. Many researches are investigated and several techniques are introduced to optimize performance and support all functions of regular expression on hardware platform. However there is very few researches in the minimization of multiple ... View full abstract»

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