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ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors

11-14 Sept. 2011

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Displaying Results 1 - 25 of 49
  • [Front cover]

    Publication Year: 2011, Page(s): c1
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  • [Title page]

    Publication Year: 2011, Page(s): ii
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  • [Title page]

    Publication Year: 2011, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2011, Page(s): iv
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  • Table of contents

    Publication Year: 2011, Page(s):v - vii
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  • Message from the conference chairs

    Publication Year: 2011, Page(s): viii
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  • Conference organizers

    Publication Year: 2011, Page(s): ix
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  • Program Committee

    Publication Year: 2011, Page(s):x - xi
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  • External referees

    Publication Year: 2011, Page(s):xii - xiii
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  • Era of customization and specialization

    Publication Year: 2011, Page(s): 3
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  • More than 50 years of parallel processing and still no easy path to speedup

    Publication Year: 2011, Page(s): 4
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  • Architectures for Green routers

    Publication Year: 2011, Page(s): 5
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  • CusComNet: A customisable network for reconfigurable heterogeneous clusters

    Publication Year: 2011, Page(s):9 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (238 KB) | HTML iconHTML

    Computer clusters equipped with reconfigurable accelerators have shown promise in high performance computing. This paper explores novel ways of customising data communication between accelerator nodes, which is often a bottleneck when scaling up the cluster size. Based on the direct connection of high speed serial links between advanced reconfigurable devices, we develop and evaluate CusComNet, a ... View full abstract»

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  • Address generation scheme for a coarse grain reconfigurable architecture

    Publication Year: 2011, Page(s):17 - 24
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1457 KB) | HTML iconHTML

    In this paper, we describe a versatile address generation scheme for distributed storage resources of a coarse grain Parallel Distributed Digital Signal Processing (PDDSP) reconfigurable architecture under development in our group. This scheme proposes the distributed address generation units (AGUs) to decouple the address generation logic with compute logic to exploit parallelism (ILP and TLP). T... View full abstract»

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  • Accelerating vision and navigation applications on a customizable platform

    Publication Year: 2011, Page(s):25 - 32
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (825 KB) | HTML iconHTML

    The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computationally demanding solutions, it is challenging to achieve high performance without sacrificing the fidelity of results or otherwise consuming excessive amounts of energy. Our goal then is to accelerate the applications in th... View full abstract»

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  • A high-performance, low-power linear algebra core

    Publication Year: 2011, Page(s):35 - 42
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (406 KB) | HTML iconHTML

    Achieving high-performance while reducing power consumption is a key concern as technology scaling is reaching its limits. It is well-accepted that application-specific custom hardware can achieve orders of magnitude improvements in efficiency. The question is whether such efficiency can be maintained while providing enough flexibility to implement a broad class of operations. In this paper, we ai... View full abstract»

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  • A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator

    Publication Year: 2011, Page(s):43 - 50
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (162 KB) | HTML iconHTML

    There is a significant demand for decimal arithmetic, especially in commercial and financial applications. Furthermore, specifications for decimal floating-point (DFP) formats and arithmetic operations have been added to the IEEE-754-2008 Standard. Hardware and software support for DFP arithmetic operations have been investigated, especially in the last decade. This paper presents a novel DFP fuse... View full abstract»

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  • Longest Prefix Match and updates in Range Tries

    Publication Year: 2011, Page(s):51 - 58
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (939 KB) | HTML iconHTML

    In this paper, we describe an IP-Lookup method for network routing. We extend the basic Range Trie data-structure to support Longest Prefix Match (LPM) and incremental updates. Range Tries improve on the existing Range Trees allowing shorter comparisons than the address width. In so doing, Range Tries scale better their lookup latency and memory requirements with the wider upcoming IPv6 addresses.... View full abstract»

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  • Low-cost hardware profiling of run-time and energy in FPGA embedded processors

    Publication Year: 2011, Page(s):61 - 68
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (269 KB) | HTML iconHTML

    This paper introduces a low-overhead hardware profiling architecture, called LEAP, that attains real-time cycle and energy profiles of an FPGA-based soft processor. A novel technique is used to associate profiling data with specific functions in a way that is area- and power-efficient. Results show that relative to a previously-published hardware profiler, our design uses up to 18× less are... View full abstract»

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  • TimeTrial: A low-impact performance profiler for streaming data applications

    Publication Year: 2011, Page(s):69 - 76
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (665 KB) | HTML iconHTML

    Finding performance bottlenecks in application-specific systems is becoming increasingly labor-intensive as the capabilities of these systems improve. The complex platforms required to meet today's high application performance demands put pressure on developers to sustain current design cycles. Application developers need better tools to diagnose performance issues that arise when utilizing real-w... View full abstract»

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  • System-level design space exploration for dedicated heterogeneous multi-processor systems

    Publication Year: 2011, Page(s):79 - 86
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (314 KB) | HTML iconHTML

    This work faces the problem of the HW/SW co-design of dedicated systems based on heterogeneous multi-processor architectures. In particular, it proposes a system-level design space exploration approach that allows the related co-design methodology to suggest an HW/SW partitioning of the application specification and a mapping of the partitioned entities onto an automatically selected heterogeneous... View full abstract»

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  • Decentralized dynamic resource management support for massively parallel processor arrays

    Publication Year: 2011, Page(s):87 - 94
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1398 KB) | HTML iconHTML

    This paper presents a hardware-supported resource management methodology for massively parallel processor arrays. It enables processing elements to autonomously explore resource availability in their neighborhood. To support resource exploration, we introduce specialized controllers, which can be attached to each of the processing elements. We propose different types of architectures for the explo... View full abstract»

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  • Hybrid data structure for IP lookup in virtual routers using FPGAs

    Publication Year: 2011, Page(s):95 - 102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (210 KB) | HTML iconHTML

    Network router virtualization has recently gained much interest in the research community, as it allows multiple virtual router instances to run on a common physical router platform. The key metrics in designing network virtual routers are (1) number of supported virtual router instances, (2) total number of prefixes, and (3) ability to quickly update the virtual table. Existing merging algorithms... View full abstract»

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  • An area-Efficient LDPC decoder for multi-standard with conflict resolution

    Publication Year: 2011, Page(s):105 - 112
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1170 KB) | HTML iconHTML

    This paper presents an area efficient decoder architecture that supports both perfectly structured and not perfectly structured LDPC codes. To verify our architecture, an area-efficient LDPC decoder that supports both China Multimedia Mobile Broadcasting (CMMB) and Digital Terrestrial/ Television Multimedia Broadcasting (DTMB) standards is developed. A solution is proposed to avoid memory access c... View full abstract»

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  • High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder

    Publication Year: 2011, Page(s):113 - 121
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (243 KB) | HTML iconHTML

    To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleaver has become a major bottleneck that limits the achievable throughput in the parallel decoders due to the massive memory conflicts. In this paper, we propose a flexible Double-Buffer based Contention-Free (DBCF) interleave... View full abstract»

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