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Proceedings 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype

24-26 June 1997

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  • Proceedings 8th IEEE International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (154 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1997, Page(s): 179
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    Freely Available from IEEE
  • Rapid prototyping of communication architectures

    Publication Year: 1997, Page(s):136 - 141
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Proposes a rapid prototyping system (RPS) focusing on interprocessor/inter-module communication. Integrated in a design environment for embedded mixed hardware/software systems, the RPS facilitates design space exploration and validation of communication links. The reprogrammable system architecture allows the prototyping of different topologies, communication types and protocols and is supported ... View full abstract»

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  • Divide and conquer approach to functional verification of PowerPC TM microprocessors

    Publication Year: 1997, Page(s):128 - 133
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Design verification engineers are one of the hottest commodities in microprocessor design. The increased complexity of these chips has nor been accompanied by an equal increase in design verification techniques. Thus, the existing workforce must work smarter in order to make up the difference. This paper outlines one of the areas in which verification engineers at the Somerset Design Center have b... View full abstract»

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  • A new approach to fault emulation

    Publication Year: 1997, Page(s):173 - 179
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Presents a hardware-based approach to fault emulation without a dedicated logic emulation system. Logic is introduced for fault injection in a targeted circuit. The logic emulator is expanded with additional hardware modules required for the fault emulation process. This method simulates the stuck-at fault model and may also be used for multiple faults and bridging faults. The implementation discu... View full abstract»

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  • Software synthesis for dynamic data flow graph

    Publication Year: 1997, Page(s):72 - 79
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Data flow graph is a useful computational model to describe the functionality of a digital system. To execute a data flow graph on a target system, it should be synthesized to the code to be compiled on the target system. Current research activities on software synthesis are mainly focused on Synchronous Data Flow (SDF) graph, which can not represent the control structure of the application. On th... View full abstract»

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  • Use of queueing network and trace-driven simulation techniques in PowerPC processor and system performance trade-off studies

    Publication Year: 1997, Page(s):122 - 127
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Presents the methodology used and the results obtained in studying design trade-offs for the PowerPC family of processors and system designs using these processors. Specifically, the effects of various cache hierarchies and multiprocessor designs on system performance are examined. Issues dealt with include the performance speedup for different multiprocessor configurations and memory subsystem de... View full abstract»

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  • Rapid prototyping of hardware systems via model reuse

    Publication Year: 1997, Page(s):150 - 156
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    The increasing productivity gap affecting the progress of electronic system design is a sufficient motivation to investigate further solutions to avoid this problem. As an immediately available solution, the application of reuse techniques is widely recognized. By reusing designs, productivity is increased because designers do not have to reinvent large portions of the design. Design reuse is beco... View full abstract»

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  • Automaton: an autonomous coverage-based multiprocessor system verification environment

    Publication Year: 1997, Page(s):168 - 172
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    The number of computation cycles used for simulation-based verification of multiprocessor systems is the available throughput of simulation. This paper presents Automaton, a verification framework for multiprocessor systems based on the state-space coverage of interacting state machines in the system components. Automaton provides focused verification of those components and minimizes the demand o... View full abstract»

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  • Macro-instruction generation for dynamic logic caching

    Publication Year: 1997, Page(s):63 - 69
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    This paper outlines the synthesis of macro-instructions for dynamically reprogrammable FPGAs so that they may be easily generated, placed, and garbage collected at run-time. An overview of a dynamic logic caching computer that uses these macro-instructions is given and their use within the's environment discussed. The synthesis of macro-instructions is illustrated with a basic example. Finally, th... View full abstract»

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  • Performance analysis for a Java-based virtual prototype

    Publication Year: 1997, Page(s):12 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    For the development of complex microelectronic systems with real-time requirements, shortened time-to-market and reduced budgets, virtual prototyping is essential for an efficient design process. These initial prototypes can be used to efficiently check design alternatives, to validate the functionality and to find time and cost critical parts of the system. To meet these requirements an initial s... View full abstract»

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  • Computing communication cost by Petri nets for hardware/software codesign

    Publication Year: 1997, Page(s):44 - 56
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (908 KB)

    This work presents a method to compute communication cost by applying Petri nets. This cost is being used to guide the hardware/software partitioning in a methodology for hardware/software codesign context, which is being developed. Petri nets are a family of formalisms sharing basic principles. Although for each purpose or detail level one appropriated formalism have to be chosen from the family,... View full abstract»

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  • Hardware in-the-loop simulation-a rapid prototyping approach for designing mechatronics systems

    Publication Year: 1997, Page(s):116 - 121
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Presents a rapid prototyping approach for the design and verification of mechatronics systems. We show the need for rapid prototyping the information processing part to perform hardware-in-the-loop simulation due to the limited modeling capability of mechanical processes. We propose the use of a graphical environment based on dataflow graphs to capture suitable algorithms. Through automatic extrac... View full abstract»

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  • A process infrastructure for architecture analysis and embedded processor development to support a technology insertion process

    Publication Year: 1997, Page(s):142 - 149
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    Commercial off-the-shelf (COTS) technology is being advocated by many as a way to reduce costs in all aspects of systems from initial development to production and field support. Embedded processors in systems, such as those found in military platforms, are examples where the use of COTS technology offers potentially large cost savings. Another important aspect of system cost is the length of time... View full abstract»

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  • KBMS-based evolutionary prototyping of software systems

    Publication Year: 1997, Page(s):80 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1032 KB)

    The development of a complex software system is a costly endeavor. Prototypes would not be “throw-aways” and much time and effort could be saved if a complex software system were developed by a series of refined and verified prototypes as the prototyper gains more and more knowledge about the functionality and performance requirements of the system being developed. To support such an e... View full abstract»

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  • Rapid prototyping of networks of asynchronous multiple functional units

    Publication Year: 1997, Page(s):157 - 166
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    The design cycle of the proposed asynchronous multiple functional unit networks, from CAD tool coding to post-layout scalability, adheres to the attributes of rapid prototyping. These attributes come in five flavors: an OOP style in CAD tools; a short design, modify, evaluate and profile cycle at the dataflow graph level; the reuse of predesigned components; effective event realization of the asyn... View full abstract»

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  • Fast board-level prototyping of a speech recognition system using virtual emulation

    Publication Year: 1997, Page(s):20 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    This paper presents the board-level prototype implementation of a complete speech recognition system. The recognition system is based on a chip set still under development and, in its final implementation, it will perform real-time isolated-word recognition of up to 1000 word templates. In this paper we show that virtual emulation is an effective approach to high-level system prototyping and verif... View full abstract»

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  • Selective focus as a means of improving geographically distributed embedded system co-simulation

    Publication Year: 1997, Page(s):58 - 62
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    When dealing with communication-intensive systems, hardware/software co-simulation usually either requires the communication to be simulated with a uniformly lour level of detail or it performs poorly. This problem manifests itself even more strongly when considering geographically distributed co-simulation, where designers take advantage of proprietary component simulation models that are made av... View full abstract»

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  • FrameKit and the prototyping of CASE environments

    Publication Year: 1997, Page(s):91 - 97
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    In this paper, we have presented FrameKit, a software platform dedicated to the rapid prototyping of CASE environment. FrameKit architecture is similar to the ECMA reference model. It focuses on the quick definition of new graphical representations, handled by a generic user interface. FrameKit also contains a development kit composed of program libraries in various languages (C, Ada and Unix shel... View full abstract»

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  • Virtual reality prototyping-a framework for the development of electronics and telecommunication products

    Publication Year: 1997, Page(s):2 - 11
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1092 KB)

    Virtual reality prototyping is a promising technology that combines the virtual reality approach to advanced modeling, simulation and user interface techniques. The technology adjoins development models of different engineering disciplines to an executable simulation model of a product. A designer, or a customer, can see, touch, hear and operate a future product before its physical implementation ... View full abstract»

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  • An algorithm for direct synthesis of formal specifications

    Publication Year: 1997, Page(s):28 - 38
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    In the last few years researchers have attempted to adopt a unified approach to the design of mixed hardware/software systems by using codesign techniques. In all the hardware/software codesign methods proposed there are usually four steps: specification of the system, testing and/or verification of the specification, partitioning and synthesis of the hardware and software parts. In this paper we ... View full abstract»

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  • Data routing in dataflow graphs

    Publication Year: 1997, Page(s):100 - 106
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    An extension to the cycle-static dataflow graph model is proposed. It is based on the insight that in current digital signal processing (DSP) applications a significant amount of time and resources is spend on the routing of the data between the processing operations. If this part of the application is do be synthesized from a specification to a software or a hardware realization both automaticall... View full abstract»

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  • Overview of the ECOS project

    Publication Year: 1997, Page(s):39 - 43
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    This paper presents methodology and tools developed for the ECOS project. The main contributions of this project in hardware/software codesign include formal specifications of a system and hardware/software partitioning. By refinement, an acyclic graph is deduced from the formal specifications of the system, and this graph is the entry point of partitioning algorithms. The ECOS framework provides ... View full abstract»

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  • Multiprocessor system development for high performance signal processing applications

    Publication Year: 1997, Page(s):107 - 114
    Cited by:  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    Developing multiprocessor systems to implement high performance signal processing algorithms can be a formidable undertaking. A process for designing multiprocessor systems, using primarily programmable processors, is proposed. This design process starts with algorithm entry and analysis, continues with functional decomposition and architecture entry, which are used to drive the algorithm to archi... View full abstract»

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