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21st International Conference on VLSI Design (VLSID 2008)

4-8 Jan. 2008

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Displaying Results 1 - 25 of 141
  • 21st International Conference on VLSI Design - Cover

    Publication Year: 2008, Page(s): c1
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  • 21st International Conference on VLSI Design - Title page

    Publication Year: 2008, Page(s):i - ii
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  • 21st International Conference on VLSI Design - Title page

    Publication Year: 2008, Page(s): iii
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  • 21st International Conference on VLSI Design - Copyright

    Publication Year: 2008, Page(s): iv
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  • 21st International Conference on VLSI Design - TOC

    Publication Year: 2008, Page(s):v - xiii
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  • Message from the General Chairs

    Publication Year: 2008, Page(s):xiv - xv
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  • Message from the Program Chairs

    Publication Year: 2008, Page(s):xvi - xvii
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  • Conference Steering Committee

    Publication Year: 2008, Page(s): xviii
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  • Conference Committee

    Publication Year: 2008, Page(s):xix - xxi
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  • Program Committee

    Publication Year: 2008, Page(s): xxii
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  • Reviewers

    Publication Year: 2008, Page(s):xxiii - xxviii
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  • Fellowships

    Publication Year: 2008, Page(s):xxix - xxxiv
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  • VLSI Design 2007 Awards

    Publication Year: 2008, Page(s): xxxv
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  • VLSI Design Conference History

    Publication Year: 2008, Page(s): xxxvi
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  • Embedded Systems Design Conference History

    Publication Year: 2008, Page(s): xxxvii
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  • Plenary Invited Keynote Speakers

    Publication Year: 2008, Page(s):xxxviii - xxxix
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (458 KB)

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Gateway to Chips: High Speed I/O Signalling and Interface

    Publication Year: 2008, Page(s):3 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB)

    The design of inputs and outputs to integrated circuits has traditionally been a straightforward task involving procurement of a specification and its implementation. In the past few technology generations design and implementation of integrated circuit I/O's have become much more complex. Just as Moore's Law predicts that functions per chip will double every 1.5-2 years to keep up with consumer d... View full abstract»

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  • DFM / DFT / SiliconDebug / Diagnosis

    Publication Year: 2008, Page(s):5 - 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (557 KB)

    Semiconductor yield has traditionally been limited by random particle-defect based issues. However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms. A key factor for not reac... View full abstract»

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  • Oversampling Analog-to-Digital Converter Design

    Publication Year: 2008, Page(s): 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    Summary form only given. Analog-to-digital converters (or sigma-delta) converters have now become routine aspects of high- performance signal processing, ranging from precision audio to RF transceivers. In this tutorial, we will present, in a systematic fashion, the basics and design aspects of delta-sigma data converters, along with a case study of a high performance ADC designed for digital audi... View full abstract»

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  • Programming and Performance Modelling of Automotive ECU Networks

    Publication Year: 2008, Page(s):8 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (559 KB)

    The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementations of different functionalities. Today, in high-end cars, it is common to have around 70 electronic control units (ECUs), each consisting of programmable processors, one or more microcontrollers and a set of sensors an... View full abstract»

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  • Architecture Exploration for Low Power Design

    Publication Year: 2008, Page(s): 11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB) | HTML iconHTML

    This tutorial will describe in detail and demonstrate an ESL design flow for architectural exploration to determine low power designs. Increasingly SoC design is driven by integrated mobile devices such as cell phones, music players and hand-held game consoles. These devices rely on standard algorithms such as H.264, 802.1 In, or JPEG2000, which allow room for innovative implementations that can r... View full abstract»

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  • Memory Design and Advanced Semiconductor Technology

    Publication Year: 2008, Page(s): 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (553 KB) | HTML iconHTML

    This tutorial will provide a bottom-up view of the changes in semiconductor memory design as we move into the nanometer regime. We begin by discussing the breakdown of scaling and the power problem. As innovation replaces classical scaling we investigate the use of stress engineering to improve device level performance. Technology challenges in lithography and interconnects are addressed. The cons... View full abstract»

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  • Scan Delay Testing of Nanometer SoCs

    Publication Year: 2008, Page(s): 13
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (526 KB)

    Delay defects that degrade performance and cause timing related reliability failures are emerging to be a major concern in nanometer technologies. Extensive at-speed functional testing to screen out such defects can be prohibitively expensive. Scan based structural delay tests are being pursued as a possible cost effective solution to this problem. However, recent research indicates that several f... View full abstract»

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  • Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips

    Publication Year: 2008, Page(s):14 - 15
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (559 KB)

    The design for manufacturing and yield (DFM&Y) is fast becoming an indispensable consideration in today's SoCs. Most current flows only consider manufacturability and yield at the lowest levels: process, layout and circuit. As such, these metrics are treated as an afterthought. With advanced process nodes, it has become increasingly expensive-and soon prohibitive-to guarantee bit level error f... View full abstract»

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  • OpenSPARC - A Scalable Chip Multi-Threading Design

    Publication Year: 2008, Page(s): 16
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    Summary form only given. This tutorial is about OpenSPARC and provides details on the first chip multi-threading 64-bit, 32-thread microprocessor made available as open source under the GNU General Public License (GPL). View full abstract»

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