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Proceedings. 1995 IEEE International Verilog HDL Conference

27-29 March 1995

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  • Proceedings. 1995 IEEE International Verilog HDL Conference

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (341 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1995
    Request permission for commercial reuse | PDF file iconPDF (38 KB)
    Freely Available from IEEE
  • Cycle simulation techniques

    Publication Year: 1995, Page(s):2 - 8
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Nowadays most hardware design is being done at a high level of abstraction, such as a hardware description language. Hence, simulation constitutes a significant part of the design verification process. We study cycle simulation techniques that could potentially speed up simulation. Then we propose various metrics to predict the performance of a cycle based simulator which uses these cycle simulati... View full abstract»

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  • Incrementally recompiling Verilog

    Publication Year: 1995, Page(s):128 - 133
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    One of the frustrations frequently encountered by users of high level design languages is the large amount of time required to process small changes in the design. This frustration is particularly acute in the final stage of hardware design when using a hardware description language like Verilog or VHDL. Since hardware models tend to be quite large and changes made quite small, any non-incremental... View full abstract»

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  • Behavior to structure: using Verilog and in-circuit emulation to teach how an algorithm becomes hardware

    Publication Year: 1995, Page(s):19 - 28
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    We present three stages of Verilog simulation (pure behavioral, mixed behavioral/structural, and pure structural), and a final stage of in-circuit emulation for translating an algorithm into hardware. Each successive stage in the translation can be derived by minor editing of the previous stage. The pure behavioral stage uses a single Verilog process to model an algorithmic state machine (ASM) usi... View full abstract»

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  • Alis: a light-weight logic synthesis for digital signal processing of audio visual

    Publication Year: 1995, Page(s):40 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    We have developed a high-speed, light-weight logic synthesis system, called Alis, with a high-level library of mathematical operation circuits for signal processing. Instead of minimizing circuit logic, we have concentrated on synthesizing better operation circuits using optimal cells of the target ASIC library because most of digital AV signal processing circuits are mathematical operation circui... View full abstract»

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  • Standardizing delay calculation in Verilog

    Publication Year: 1995, Page(s):49 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Verilog HDL and PLI provide all the necessary means for accurate delay modeling and calculation. However, appropriate use of a delay calculator is often problematic due to the multitude of libraries and delay models used in a single design and the lack of explicit standards in delay specifications. This paper is intended to set a standard, not to provide a new in-depth method. The basic delay mode... View full abstract»

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  • Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC

    Publication Year: 1995, Page(s):67 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    This paper describes the design and validation of a complex ASIC through the use of Verilog HDL. The CMC is an interface circuit for ATM cells, part of a 2.5 Gb/s switching fabric. Its main function is serial to parallel and parallel to serial data conversion; another features like VPINCI translation, cell counting, insertion and extraction from an external microprocessor are also included. The va... View full abstract»

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  • A comprehensive pre-RTL IC design methodology

    Publication Year: 1995, Page(s):119 - 126
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    Complex integrated circuit (IC) designers must make design decisions to meet the functional and performance requirements of their specific ICs prior to register-transfer level (RTL) coding. CMEG, a comprehensive pre-RTL IC design methodology, is described. It is illustrated through an example of an image processing algorithm, and is compared against hardware description language and behavioral syn... View full abstract»

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  • Writing style for architectural synthesis

    Publication Year: 1995, Page(s):106 - 113
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    An encapsulated writing style of Verilog is described together with models for a corresponding scheduler and synthesizer. The method provides a middle ground between synthesis from behavioral specifications, which implies decisions too difficult for architectural synthesis, and synthesis from pure structural specifications, which necessitates providing full details of the controller and netlist. T... View full abstract»

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  • Observing your Verilog-XL simulation from 30,000 feet: using high level views of simulations to improve debug productivity

    Publication Year: 1995, Page(s):84 - 89
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    Describes a method to improve simulation debugging throughput by the examination of simulation results at higher levels of abstraction than are generally used by most designers today. As ASIC designs become more and more complex, these kind of techniques will play an increasingly important role in the faster detection and repair of intricate problems within large design descriptions. This paper ex... View full abstract»

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  • An integrated environment for HDL verification

    Publication Year: 1995, Page(s):9 - 18
    Cited by:  Papers (7)  |  Patents (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    The functional verification of a digital design is an expensive step in the design process. As designs become more complex, simulation is challenged throughout the design and verification process, both at the low level (implementation verification), to show that a low level implementation implements a higher-level specification, and at the high level (design verification), to show that a design co... View full abstract»

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  • Compiling Verilog into timed finite state machines

    Publication Year: 1995, Page(s):32 - 39
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    The lack of formal semantics for HDLs has made it hard to make a formal bridge between simulation tools based on HDLs and synthesis/verification tools based on finite state machines. We address the problem of finding a larger subset of Verilog HDL (which includes timing constructs) and a systematic way of extracting FSMs from programs built using the subset. Using timed FSMs as the target language... View full abstract»

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  • Measuring HDL-based design productivity: an experimental comparison

    Publication Year: 1995, Page(s):44 - 48
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    Two process models for top-down HDL-based design are developed in order to measure HDL-based design productivity. A sorting algorithm is used as a benchmark to experience various design activities in HDL entry and mixed entry design process models. We measure the effort (time) required for each design activity and analyze the “effort-distribution” over various design activities. We als... View full abstract»

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  • Verilog modeling and simulation of a communication coprocessor for multicomputers

    Publication Year: 1995, Page(s):58 - 66
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    We describe the Verilog modeling and design of a static fault-tolerant hardware router for use in a communication coprocessor in distributed memory multicomputer. The coprocessor employs a wormhole routing technique for packets. Virtual channels are used to better utilize the communication bandwidth offered by the physical links. The router implements a fault-tolerant routing algorithm, which can ... View full abstract»

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  • Verilog-based performance evaluation of a multiprocessor system

    Publication Year: 1995, Page(s):73 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    We present the outcome of an exercise to model, in Verilog HDL, a non-homogeneous, pyramid-organised, multiprocessor system. The model has been constructed to represent, at varying degrees of detail, the dynamic behaviour of the system and has subsequently been verified and calibrated against components of the realised system. The paper discusses the performance of the model, the type of results a... View full abstract»

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  • A virtual memory management scheme for simulation environment

    Publication Year: 1995, Page(s):114 - 118
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A virtual memory management scheme is proposed for integrating large memory in the simulation environment. This is a novel extension to the Verilog-XL simulator from Cadence Design Systems. The scheme provides a user-transparent mechanism to instantiate a large chunk of memory without being limited by the main-memory of the simulating machine View full abstract»

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  • A Verilog preprocessor for representing datapath components

    Publication Year: 1995, Page(s):90 - 98
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Describes research leading to the generation of a preprocessor for the Verilog hardware description language. The function of this preprocessor is to support repeated feature instances in a Verilog description for a digital system. Repeated features most commonly occur in the description of datapaths, where iterative structures like adders, multipliers and muxes are the basic building blocks. Cita... View full abstract»

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  • Practical code coverage for Verilog

    Publication Year: 1995, Page(s):99 - 104
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The ability to detect sections of code that have not been executed in a program or design has always been desired by hardware designers, since unexecuted code is clearly untested code. Unfortunately, there have been virtually no practical mechanisms for doing so. Given the combinatorial number of input possibilities for even a moderate design, exhaustive coverage obviously exceeds the capabilities... View full abstract»

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