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14th IEEE Symposium on High-Performance Interconnects (HOTI'06)

Date 23-25 Aug. 2006

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Displaying Results 1 - 25 of 29
  • 14th IEEE Symposium on High-Performance Interconnects - Cover

    Publication Year: 2006, Page(s): c1
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  • 14th IEEE Symposium on High-Performance Interconnects - Title

    Publication Year: 2006, Page(s):i - iii
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  • 14th IEEE Symposium on High-Performance Interconnects - Copyright

    Publication Year: 2006, Page(s): iv
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  • 14th IEEE Symposium on High-Performance Interconnects - TOC

    Publication Year: 2006, Page(s):v - vi
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  • General Chairs' message

    Publication Year: 2006, Page(s): vii
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  • General Co-Chairs' Message

    Publication Year: 2006, Page(s): viii
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  • Program Committee

    Publication Year: 2006, Page(s): ix
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  • Organizing Committee

    Publication Year: 2006, Page(s): x
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  • Technical Programming Committee

    Publication Year: 2006, Page(s): xi
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  • Keynote Speaker I

    Publication Year: 2006, Page(s): xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (461 KB)

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. View full abstract»

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  • Keynote Speaker II

    Publication Year: 2006, Page(s): xiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. View full abstract»

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  • Tutorial I

    Publication Year: 2006, Page(s):xiv - xv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB) | HTML iconHTML

    Provides an abstract of the presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Tutorial II

    Publication Year: 2006, Page(s): xvi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Provides an abstract of the presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Tutorial III

    Publication Year: 2006, Page(s): xvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Provides an abstract of the presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Tutorial IV

    Publication Year: 2006, Page(s): xviii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (463 KB)

    Provides an abstract of the presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • Loosely Coupled TCP Acceleration Architecture

    Publication Year: 2006, Page(s):3 - 8
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (134 KB) | HTML iconHTML

    We present a novel approach for scalable network acceleration. The architecture uses limited hardware support and preserves protocol processing flexibility, combining the benefits of TCP offload and onload. The architecture is based on decoupling the data movement functions, accelerated by a hardware engine, from complex protocol processing, controlled by an isolated software entity running on a c... View full abstract»

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  • Network I/O Acceleration in Heterogeneous Multicore Processors

    Publication Year: 2006, Page(s):9 - 14
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Chip multiprocessor (CMP) architectures are fast becoming the dominant design for general purpose processors. Whereas current generation server and desktop processors use homogenous CMP architectures, network processors (NPs) have used heterogeneous CMP architectures for years. At the same time, the failure of network stacks in traditional processors to scale with increased network bandwidths has ... View full abstract»

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  • A Case Study in I/O Disaggregation using PCI Express Advanced Switching Interconnect (ASI)

    Publication Year: 2006, Page(s):15 - 24
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB) | HTML iconHTML

    Decoupling the processor and I/O subsystem provides immense benefits that include high availability, efficient allocation and cost-effective upgrade of system resources. Such a disaggregation model calls for a high-performance interconnect to isolate the processor and I/O subsystem domains, yet provide the veneer of a single system. PCI express (PCIe) is one such interconnect and is becoming the d... View full abstract»

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  • Designing Full-Connectivity WDM Optical Interconnects with Reduced Switching and Conversion Complexity

    Publication Year: 2006, Page(s):25 - 30
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    Most existing wavelength division multiplexing (WDM) optical interconnects make use of a large number of switching elements and require wide-range tunable wavelength converters to support full-connectivity among inputs and outputs. This results in complex and expensive designs. In this paper, we propose new full-connectivity single-stage and multi-stage WDM optical interconnects with and reduced h... View full abstract»

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  • A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems

    Publication Year: 2006, Page(s):31 - 36
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (227 KB) | HTML iconHTML

    As bit rates increase, optical interconnects based high-performance computing (HPC) systems improve performance by increasing the available bandwidth (using wavelength-division multiplexing (WDM) and space-division multiplexing (SDM)) and decreasing power dissipation as compared to traditional electrical interconnects. While static allocation of wavelengths (channels) in optical interconnects prov... View full abstract»

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  • Strictly Nonblocking Multicasting WDM Optical Cross Connects Using Multiwavelength Converters

    Publication Year: 2006, Page(s):37 - 44
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (174 KB) | HTML iconHTML

    In this paper, we propose new strictly nonblocking multicast capable optical cross connects (MC-OXCs) architectures that exploit the potential of multi-wavelength converters (MWCs). An MWC is capable of simultaneously replicating a signal on an input wavelength to several output wavelengths. We investigate two families of MCOXCs based on use of full- and limited-range MWCs, and present a number of... View full abstract»

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  • ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform

    Publication Year: 2006, Page(s):45 - 51
    Cited by:  Papers (6)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (545 KB) | HTML iconHTML

    We propose ExpressEther as Ethernet-based virtualization technology for a reconfigurable hardware platform. It groups modularized hardware resources interconnected by an Ethernet, and transports a PCI express (PCIe) packet between the grouped modules by encapsulating it into an Ethernet frame. The configuration of the group is dynamically reconfigured by an Ethernet connection, followed by standar... View full abstract»

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  • Memory Scalability Evaluation of the Next-Generation Intel Bensley Platform with InfiniBand

    Publication Year: 2006, Page(s):52 - 60
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB) | HTML iconHTML

    As multi-core systems gain popularity for their increased computing power at low-cost, the rest of the architecture must be kept in balance, such as the memory subsystem. Many existing memory subsystems can suffer from scalability issues and show memory performance degradation with more than one process running. To address these scalability issues, fully-buffered DIMMs have recently been introduce... View full abstract»

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  • A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing

    Publication Year: 2006, Page(s):61 - 66
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (395 KB) | HTML iconHTML

    This paper presents a reconfigurable architecture for high-speed content-based routing. Our architecture goes beyond simple pattern matching by implementing a parsing engine that defines the semantics of patterns that are parsed within the data stream. Defining the semantics of patterns allows for more accurate processing and routing of packets using any fields that appear within the payload of th... View full abstract»

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  • Fast Buffer Memory with Deterministic Packet Departures

    Publication Year: 2006, Page(s):67 - 72
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB) | HTML iconHTML

    High-performance routers need to store temporarily a large number of packets in response to congestion. DRAM is typically used to implement the needed packet buffers, but DRAM devices are too slow to match the bandwidth requirements. To bridge the bandwidth gap, a number of hybrid SRAM/DRAM packet buffer architectures have been proposed (S. Iyer and N. Mckeown, 2002) (S. Kumar et al., 2005). These... View full abstract»

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