The COB stack DRAM cell at technology node below 100 nm-scaling issues and directions

The scaling of the 8F/sup 2/ COB stack DRAM cell down to 70-nm technology node is described. Issues and possible solutions regarding critical points, such as the difficulty in achieving sufficient memory cell capacitance, degraded cell transistor performance, and increased junction leakage current at storage node are investigated. Although its unit cell size is bigger than those of open bit line cell architectures, the 8F/sup 2/ COB stack cell can be the most suitable technology for 70-mn DRAM technology node due to its excellent noise immunity and large capacitor area.