The effect of gate orientation on fault detection

Real defects (e.g. stuck-at or bridging faults) in VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. When a resistive (nonzero) fault model is used in fault detection, the gate orientation plays an important role. In this work, we discuss how a logically symmetrical gate may show electronically nonsymmetrical behavior and how such a property influences fault detection and test pattern generation of digital VLSI circuits.