Low-Power CMOS Super-Regenerative Receiver With a Digitally Self-Quenching Loop

A 500 MHz super-regenerative receiver (SRR) with a digitally self-quenching loop (DSQL) is designed for low-power/high-data-rate applications. The DSQL replaces the envelope detector used in a conventional SRR and minimizes the overall power consumption by generating a self-quench signal digitally for a super-regenerative oscillator. The receiver is fabricated using a 0.13 μm CMOS process. The chip size is 0.7 mm
²
and the minimum energy usage is 0.09 nJ/b with a supply voltage of 1 V at a data rate of 10 Mbps. The measured sensitivity is - 76 dBm.