Design and Characterization of a Multilevel DRAM

Multilevel DRAM (MLDRAM) increases the storage density of DRAMs by using more than two signal levels in the data storage cells. Our MLDRAM uses reference and data cell signals that are generated in the cell array using charge sharing. The single-step sensing method uses multiple reference signals in parallel. We describe an operational 19200-cell MLDRAM test chip in 1.8-V, 180-nm mixed-signal CMOS that allows 1, 1.5, 2, 2.25, and 2.5 bits-per-cell operation using 2, 3, 4, 5, and 6 data signal levels, respectively. Characterization features include a partitioned memory array with four different data cell sizes, two sense amplifier sizes, and selective bitline shielding. New tests were developed using an MLDRAM fault model covering basic functionality, retention time, multilevel march, inter-bitline coupling and cell plate voltage bump tests. We show that, with short bitlines, MLDRAM's noise margins can be similar to DRAM's to more reliably store two bits in a 1T1C cell.