Quadrature Direct Digital Frequency Synthesizer Using FPGA

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Such system is based on a classical DDFS structure. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The system is implemented using FPGA with 3.3 V supply voltage. The power consumption is 3.96 mW. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz