A "defect level versus cost" system tradeoff for electronics manufacturing

Both cost and quality are important features when manufacturing today's high-performance electronics. Unfortunately, the two design goals (low) cost and (high) quality are somewhat mutually exclusive. High testing effort (and thus, quality) comes with a considerable cost, and lowering test activities has significant impact on the delivered quality. In this paper, we present a new structured search method to obtain the best combination of these two goals. It features a Petri-net oriented cost/quality modeling approach and uses a Pareto chart to visualize the results. The search for the Pareto-optimal points is done by means of a genetic algorithm. With our method, we optimize a manufacturing process for a global positioning system (GPS) front end. The optimized process clearly outperformed the standard fabrication process.