A novel ROM-less direct digital frequency synthesizer based on Chebyshev polynomial interpolation

In this paper a novel ROM-less direct digital frequency synthesizer (DDFS) is introduced. The phase-to-sine mapping section of this new scheme is designed based on approximation of the first half cycle of a cosine signal by a fourth order Chebyshev polynomial. The spurious free dynamic range (SFDR) of the proposed method is 64.2 dBc while the maximum achievable SFDR is theoretically obtained equal to 66.2 dBc. The proposed method is also implemented using the Xilinx Vertex-II FPGA and the experimental results exhibit the maximum clock frequency around 25 MHz.