Impact of pad and gate parasitics on small-signal and noise modeling of 0.35 /spl mu/m gate length MOS transistors

Microwave noise performance of p and n-type MOSFETs fabricated on the. same wafer was investigated in order to study the effect of the pad and gate parasitic circuit elements on noise performance. At low drain currents, the gate parasitic circuit was involved in the modeling to explain the observed kinks and loops in the s-parameters. Simulation of the noise parameters for p and n-type devices, measured in the 2-26 GHz frequency range, was performed by using extracted small-signal models of the transistor in connection with parasitic pad and gate circuits. Under the bias far from the optimal one, the additional parasitic inductance in the gate circuit was found responsible for the degradation of the noise performance by exhibiting peaks in the noise parameters.