Dependability analysis of a fault-tolerant processor

Advances in semiconductor technology have improved the performance of integrated circuits, in general, and microprocessors, in particular, at a dazzling pace. Although, smaller transistor dimensions, lower power voltages and higher operating frequencies have significantly increased the circuit sensitivity to transient and intermittent faults. In this paper we present the architecture of a fault-tolerant processor and analyze its dependability with the aid of a generalized stochastic Petri net (GSPN) model. The effect of transient and intermittent faults is evaluated. It is concluded that fault tolerance mechanisms, usually employed by custom designed systems, have to be integrated into commercial-off-the-shelf (COTS) devices, in order to mitigate the impact of higher rates of occurrence of the transient and intermittent faults.