A full differential low voltage low power high speed current comparator

A full differential low-voltage, low-power, and high-speed CMOS current comparator has been designed. The circuit is implemented using 0.5 /spl mu/m CMOS technology and simulated using HSPICE. The comparison is performed in just one clock cycle with a sampling rate of 600 MHz, and can sense currents down to 0.1 /spl mu/A (without considering the offset). The amount of offset obtained using Monte Carlo simulation is absolutely less than 0.4 /spl mu/A for 95% of the cases. Power dissipation is less than 1 mW.