Signal probability calculation in Boolean functions using graph oriented realization

This paper presents a method for signal probability calculation in digital circuits, using graph-oriented realization (GOR) (Ghaznavi-Ghoushchi, 1998). It starts from BDD cutset graphs, and computes the probability by incorporating the "high"-terminated cutsets. The correlations between cutsets are accounted for. Theories and rules necessary for generalization of the method are given, and the method can be readily incorporated in CAD tools for digital design.