Challenges of CMOS scaling at below 0.1 /spl mu/m

Over the last two decades, CMOS scaling has been the main driver of the electronics industry. During the last few years, the pace of scaling has been accelerating, and we are approaching some fundamental limits. In this paper, some of the key challenges of CMOS scaling, as we move into the 0.1 /spl mu/m generation and beyond, are reviewed. They include challenges faced in short channel effects, gate oxide scaling, I/sub off/ and low voltage operation, metallization, and reliability. A few of the potential solutions to some of these problems are discussed. They include introduction of SOI and novel structures, high-k gate dielectrics, strained Si layers on SiGe, and low-T operation.