Reducing the power consumption in FPGAs with keeping a high performance level

Power consumption is becoming an important constraint in VLSI design because of the increase of wireless and portable battery powered applications. On the other hand, the use of Field Programmable Gate Arrays (FPGAs) has been increasing largely due to the ability to rapidly develop prototypes with reduced development times and costs. A well known technique for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization is used to save power even when it increases silicon area. This technique implemented in FPGAs can represent several advantages. Since D-type flip-flops (DFFs) are for free inside each logic cell, pipeline architectures match naturally in FPGAs. Finally, some commercial FPGAs can work using a low supply voltage with no dramatic performance degradation.