A generalized prediction method for modified memory-based high throughput VLC decoder design

Variable-length code (VLC) is the most popular data-compression technique which has been used in many data-compression standards, such as JPEG, MPEG-2, and H.263. In this paper, we present a new memory-based tree-search algorithm and very large scale integration architecture for VLC decoders which can achieve very high decoding throughput performance. Different coding tables can be implemented by simply changing the contents of the memory without changing the system hardware. The coding table is mapped onto a memory whose space requirement has been minimized by using a new tree data structure and efficient memory-mapping strategy. In addition, we break the recursive dependency of iterative searching operations by predicting method. The proposed algorithm and architecture can predict the searching node and perform parallel operations. As a result, the decoding throughput rate can be enhanced to about three to eight times more than previously announced architectures. The proposed architecture mainly consists of memory modules and simple arithmetic unit. Based on 0.6-/spl mu/m single poly triple metal CMOS technology and MPEG-2 VLC table-15, the decoder system achieves average decoding throughput rate of 720 Mbits/s at 3 V and a 100-MHz clock rate.