RST cache memory design for a highly coupled multiprocessor system

The implementation of a coherence protocol and the cache-memory architecture for a Clipper-based multiprocessor prototype is described. The Clipper was chosen for its high-performance features: fast clock speed, internal caches, internal dual buses, sophisticated pipelining system, and integrated execution units. Previous experience in which a common bus caused the main performance bottleneck motivated the use of a private cache for each processor. The coherence protocol, called reduced state transitions (RST), is a modification of the Dragon protocol. In particular, the high performance of RST results from sophisticated architectural solutions, such as the use of buffers and overlapping a processor operation and a bus transaction. Additional performance improvement stems from the balance between several cache factors and careful tuning obtained by means of a simulation phase.<
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