Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications

In this paper we present the results of a design-space exploration for a classification algorithm with respect to the inherent parallelism of the CoreVA CPU. The CoreVA is a configurable VLIW processor which has been mainly designed for energy-constrained applications. Energy-efficient signal-processing is essential for real-time applications on wireless body sensors (WBSs). Using a velocity-estimation algorithm for a runner as an example, we show which hardware and algorithm configurations perform best in respect to classification accuracy, runtime and energy consumption. We obtained 9 Pareto-optimal configurations out of 504 simulations. The highest classification accuracy of 93.4% requires 34687 clock cycles and has an energy consumption of 1.559 μJ. The lowest energy requirements of 0.015μJ per classification are observed with a Pareto-optimal configuration at 76.3% accuracy. The three-issue VLIW configuration shows the best results with respect to the area-energy trade-off.