Design and analysis of RF CMOS transceivers for wireless applications in 0.18-µm CMOS Technology

The paper investigates the feasibility of the latest CMOS technology for the design and analysis of the emerging 60-GHz wireless applications. Recent developments in millimeter-wave CMOS systems have begun to address the integration of building blocks to form transceivers. With the availability of 7 GHz of unlicensed spectrum around 60 GHz, there is growing interest for new consumer applications requiring very high data-rate wireless transmission. In addition to these generic challenges and high frequency operation and a low-noise design, transceivers operating at these frequencies must deal with three critical issues related to the local oscillator generation, division, and distribution. It is therefore important to develop “synthesizer friendly” transceivers so as to alleviate these issues. A “half-RF” architecture incorporating a polyphase filter in the signal path to allow the use of a local oscillator frequency equal to half the input frequency. The receiver performs 90° phase shift and two downconversion steps to produce quadrature baseband outputs. The transmitter upconverts the quadrature baseband signals in two steps, applies the results to a polyphase filter, and sums its outputs. The transceiver operating at 1.8 V power supply & achieves a noise figure of 15.8 dB at 60 GHz and consumes 135mW of power.