Impact of low-doped substrate areas on the reliability of circuits subject to EFT events

External stresses, such as those generated due to Electrical Fast Transient (EFT) events, generate over-voltages which may result in reliability failures at the IClevel either in the form of recoverable or permanent damage of the IC. In the present paper, the relationship between the technology characteristics within a design framework and the permanent failures that such an EFT event can produce are discussed. Solutions to minimize the impact of such EFT events are presented.