A TaSi/sub 2/ masked and plasma etched self-aligned SOS FET

A self-aligned Ta silicide poly-silicon gate SOS junction field effect transistor is described. The active N-layer was formed by phosphorus ion implantation into high resistivity silicon on sapphire resulting in an electron density of about 5/spl times/10/sup 16//cm/sup 3/. Poly-silicon film was then deposited on SOS by CVD method at 700/spl deg/C. This film was undoped as deposited which was subsequently implanted with boron ion to form P/sup +/ layer. Ta silicide film with thickness of 2000 A was deposited on this P/sup +/ poly- silicon film by spattering. The major processes for fabricating the self-aligned gate JFET include the definition of the gate region followed by phosphorus implantation to from N/sup +/ contact to source and drain electrodes. The I-V characteristics of the junction FET so fabricated showed complete channel pinch-off with DC transconductance varying from 0.1 to 2.5 ms/mm gate width depending on the channel conductance.