A reduced-area low-power low-voltage single-ended differential pair

In analog very large scale integration (VLSI), a high computational density is important. Area savings can be obtained by operating the MOS transistor in the triode region, thus exploiting its symmetrical nature. Applying this theory to a single-ended differential pair results in an area reduction of up to a factor 1.5, which can be significant, e.g., for neural networks, where the basic cells are repeated many times on a single chip. The proposed circuit also has advantages with respect to low-power and low-voltage operation.