Evaluations for a highly scalable, reliable vertical channel SONOS memory

A vertical channel SONOS memory, which is compatible with current CMOS process and has four physical storage nodes per unit area, is fabricated and electrically evaluated. Comparing with a planar device, the array cell tuning is much easier since the channel length is no longer limited by array area. After reviewing key performances including program/erase (P/E) speeds, second bit effect, program disturbance, endurance, and retention on a NOR-type array, it is found that four physical bits/cell is hard to achieve due to a serious program disturb. Unavoidable high energy 2
^nd
hot electron between neighbor cells is identified as the root cause. In this paper, operation procedures and array layouts, which are suitable for three physical bits per cell (3bits/cell), is then proposed.