A high efficiency Si LDMOS Doherty power amplifier with optimized linearity

This paper presents a high efficiency uneven UMTS Doherty power amplifier (DPA) based on Si LDMOS technology. An optimum output combining network was designed to enhance the efficiency at backoff power. High efficiency Si LDMOS transistors were used for the DPA design. The designed DPA has a maximum output power of P
_sat
=39.7 dBm (9.4 W). A maximum drain efficiency of ¿
_max
=54% (PAE
_max
=40%) was measured. The efficiency was maintained above ¿=40% (PAE =36%), over 6 dB backoff, and above ¿=32% (PAE=30%), over 9 dB backoff, relative to the maximum (saturated) output power. The designed PA was experimentally optimized to enhance its linearity. For a 1-carrier W-CDMA test signal, an ACPR of -44 dBc was measured at an average output power of P
_out
=30.7 dBm.