Efficient CMOS driver-receiver pair with low-swing signaling for on-chip interconnects

This paper describes the design of a symmetric low-swing driver-receiver pair (mj-sib) for driving signals on the global interconnect lines. When implemented on a 0.13 mum CMOS 1.2 V technology, mj-sib scheme reduces energy-delay product by 41.7% (at the receiver load of 0.25 pF) and has 38.8% lower delay when compared with a counterpart asymmetric low-swing signaling scheme. Also, mj-sib topology has 14.2% lower energy-delay product and has 36% lower active area (50.25 mum
²
) when compared with other symmetric low-swing signaling structure. The key advantages of the proposed signaling scheme is that it requires only one power supply and threshold voltage, hence significantly reducing the design complexity.