Analysis of latchup and parasitic effects in merged BiCMOS structures

Latchup and performance degradation due to the parasitic elements in merged BiCMOS structures are studied. Circuit simulations using HSPICE and analytical characterisation are used to describe the parasitic components and model their effects on the output voltage switching characteristics and delay time. A latchup factor is defined to relate the degree of performance degradation to the device and key circuit parameters.<
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